公开(公告)号：US11475960B2

公开(公告)日：2022-10-18

申请号：US17306266

申请日：2021-05-03

申请人： STMicroelectronics S.r.l. ,  STMicroelectronics International N.V.

发明人： Fabio Enrico Carlo Disegni ,  Laura Capecchi ,  Marcella Carissimi ,  Vikas Rana ,  Cesare Torti

IPC分类号： G11C13/00 ,  G11C16/10 ,  G11C7/06 ,  G11C16/08 ,  G11C16/24 ,  G11C16/28 ,  G11C16/30 ,  G11C16/32

摘要： An embodiment non-volatile memory device includes an array of memory cells in rows and columns; a plurality of local bitlines, the memory cells of each column being coupled to a corresponding local bitline; a plurality of main bitlines, each main bitline being coupleable to a corresponding subset of local bitlines; a plurality of program driver circuits, each having a corresponding output node and injecting a programming current in the corresponding output node, each output node coupleable to a corresponding subset of main bitlines. Each program driver circuit further includes a corresponding limiter circuit that is electrically coupled, for each main bitline of the corresponding subset, to a corresponding sense node whose voltage depends, during writing, on the voltage on the corresponding main bitline. Each limiter circuit turns off the corresponding programming current, in case the voltage on any of the corresponding sense nodes overcomes a reference voltage.

公开(公告)号：US09990245B2

公开(公告)日：2018-06-05

申请号：US14951639

申请日：2015-11-25

申请人： STMICROELECTRONICS INTERNATIONAL N.V. ,  STMICROELECTRONICS S.R.L.

发明人： Om Ranjan ,  Fabio Enrico Carlo Disegni

IPC分类号： G06F11/00 ,  G06F11/07 ,  G06F11/08 ,  G06F11/16 ,  G11C29/42 ,  G11C29/02 ,  G11B20/18 ,  G06F11/10 ,  G11C29/04

CPC分类号： G06F11/079 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/076 ,  G06F11/0772 ,  G06F11/08 ,  G06F11/1004 ,  G06F11/16 ,  G11B2020/1843 ,  G11C29/02 ,  G11C29/04 ,  G11C29/42

摘要： An electronic device includes a memory having memory locations being subject to transient faults and permanent faults, and a fault detection circuit coupled to the memory. The fault detection circuit is configured to read the memory locations at a first time, and determine a first fault count and fault map signature including the transient and permanent faults at the first time based upon reading the plurality of memory locations, and to store the first fault count and fault map signature. The fault detection circuit is configured to read the memory locations at a second time and determine a second fault count and fault map signature including the transient and permanent faults at the second time based upon reading the memory locations, and compare the stored first fault count and fault map signature with the second fault count and fault map signature to determine a permanent fault count.

公开(公告)号：US11380393B2

公开(公告)日：2022-07-05

申请号：US17129016

申请日：2020-12-21

申请人： STMicroelectronics International N.V.

发明人： Maurizio Francesco Perroni ,  Fabio Enrico Carlo Disegni ,  Massimo Caruso ,  Cesare Torti

IPC分类号： G11C11/00 ,  G11C13/00

摘要： An embodiment non-volatile memory device includes an array of memory cells arranged in rows and columns; a plurality of local bitlines; and a plurality of main bitlines, each main bitline being coupleable to a corresponding subset of local bitlines. The memory cells of each column are coupled to a corresponding local bitline. The memory device further includes a column decoder, which can be controlled electronically so as to couple each main bitline to a selected local bitline of the corresponding subset of local bitlines. The column decoder couples each main bitline to two different points of the corresponding selected local bitline.

公开(公告)号：US20210366554A1

公开(公告)日：2021-11-25

申请号：US17306266

申请日：2021-05-03

申请人： STMicroelectronics S.r.l. ,  STMicroelectronics International N.V.

发明人： Fabio Enrico Carlo Disegni ,  Laura Capecchi ,  Marcella Carissimi ,  Vikas Rana ,  Cesare Torti

IPC分类号： G11C16/10 ,  G11C16/28 ,  G11C16/08 ,  G11C16/24 ,  G11C16/30 ,  G11C16/32 ,  G11C7/06

摘要： An embodiment non-volatile memory device includes an array of memory cells in rows and columns; a plurality of local bitlines, the memory cells of each column being coupled to a corresponding local bitline; a plurality of main bitlines, each main bitline being coupleable to a corresponding subset of local bitlines; a plurality of program driver circuits, each having a corresponding output node and injecting a programming current in the corresponding output node, each output node coupleable to a corresponding subset of main bitlines. Each program driver circuit further includes a corresponding limiter circuit that is electrically coupled, for each main bitline of the corresponding subset, to a corresponding sense node whose voltage depends, during writing, on the voltage on the corresponding main bitline. Each limiter circuit turns off the corresponding programming current, in case the voltage on any of the corresponding sense nodes overcomes a reference voltage.

公开(公告)号：US20210193221A1

公开(公告)日：2021-06-24

申请号：US17129016

申请日：2020-12-21

申请人： StMicroelectronics International N.V.

发明人： Maurizio Francesco Perroni ,  Fabio Enrico Carlo Disegni ,  Massimo Caruso ,  Cesare Torti

IPC分类号： G11C13/00

摘要： An embodiment non-volatile memory device includes an array of memory cells arranged in rows and columns; a plurality of local bitlines; and a plurality of main bitlines, each main bitline being coupleable to a corresponding subset of local bitlines. The memory cells of each column are coupled to a corresponding local bitline. The memory device further includes a column decoder, which can be controlled electronically so as to couple each main bitline to a selected local bitline of the corresponding subset of local bitlines. The column decoder couples each main bitline to two different points of the corresponding selected local bitline.