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公开(公告)号：US08878710B2
公开(公告)日：2014-11-04
申请号：US13677674
申请日：2012-11-15
Applicant: STMicroelectronics International N.V.
Inventor： Ankur Bal , Neha Bhargava , Anupam Jain
Abstract: In an embodiment, a set of input samples are filtered to provide a set of filtered samples using an N-tap filter. A steady-state-response-output sample of the N-tap filter is determined from a N/2th sample of the set of filtered samples.
Abstract translation: 在一个实施例中，对一组输入样本进行滤波，以使用N抽头滤波器提供一组滤波样本。 N抽头滤波器的稳态响应输出样本由滤波样本集合的第N / 2个样本确定。
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Patent Agency Ranking
2.发明授权公开(公告)号：US09780803B1
公开(公告)日：2017-10-03
申请号：US15266445
申请日：2016-09-15
Applicant: STMicroelectronics International N.V.
Inventor： Ankur Bal , Chandrajit Debnath , Neha Bhargava
Abstract: A built-in self-test (BIST) circuit is provided for testing an analog-to-digital converter (ADC). A multi-order sigma-delta (ΣΔ) modulator has an input that receives an input signal, a first output generating analog test signal derived from the input signal and applied to an input of the ADC and a second output generating a binary data stream. A digital recombination and filtering circuit has a first input that receives the binary data stream and a second input that receives a digital test signal output from the ADC in response to the analog test signal. The digital recombination and filtering circuit combines and filters the binary data stream and digital test signal to generate a digital result signal including a signal component derived from an error introduced by operation of the ADC. A correlation circuit is used to isolate that error signal component.
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公开(公告)号：US10050606B2
公开(公告)日：2018-08-14
申请号：US15632202
申请日：2017-06-23
Applicant: STMicroelectronics International N.V.
Inventor： Neha Bhargava , Ankur Bal
Abstract: A polyphase decimation FIR filter apparatus including a modulo integrator circuit configured to integrate input samples and to provide integrated input samples; and a polyphase FIR filter circuit configured to process the integrated input samples, the polyphase FIR filter circuit including a plurality of multiplier accumulator circuits, each configured to accumulate products of coefficients and respective integrated signal samples, wherein each of the multiplier accumulator circuits receives a subset of FIR filter coefficients, wherein the FIR filter coefficients are derived as the nth difference of original filter coefficients, where n is a number of integrators in the integrator circuit, and wherein the FIR filter circuit is configured to perform computation operations with modulo arithmetic.
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公开(公告)号：US20160182014A1
公开(公告)日：2016-06-23
申请号：US14573055
申请日：2014-12-17
Applicant: STMicroelectronics International N.V.
Inventor： Neha Bhargava , Ankur Bal
IPC: H03H17/02
CPC classification number: H03H17/0664 , H03H17/0275 , H03H2017/0245
Abstract: A polyphase decimation FIR filter apparatus including a modulo integrator circuit configured to integrate input samples and to provide integrated input samples; and a polyphase FIR filter circuit configured to process the integrated input samples, the polyphase FIR filter circuit including a plurality of multiplier accumulator circuits, each configured to accumulate products of coefficients and respective integrated signal samples, wherein each of the multiplier accumulator circuits receives a subset of FIR filter coefficients, wherein the FIR filter coefficients are derived as the nth difference of original filter coefficients, where n is a number of integrators in the integrator circuit, and wherein the FIR filter circuit is configured to perform computation operations with modulo arithmetic.
Abstract translation: 一种多相位抽取FIR滤波器装置，包括：模积分器电路，被配置为集成输入采样并提供集成的输入采样; 以及多相FIR滤波器电路，被配置为处理所述积分输入样本，所述多相FIR滤波器电路包括多个乘法器累加器电路，每个乘法器累加器电路被配置为累积系数乘积和相应的积分信号采样，其中每个乘法器累加器电路接收子集 的FIR滤波器系数，其中FIR滤波器系数被导出为原始滤波器系数的第n个差，其中n是积分器电路中的积分器的数量，并且其中FIR滤波器电路被配置为通过模运算执行计算操作。
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公开(公告)号：US10050607B2
公开(公告)日：2018-08-14
申请号：US14573055
申请日：2014-12-17
Applicant: STMicroelectronics International N.V.
Inventor： Neha Bhargava , Ankur Bal
Abstract: A polyphase decimation FIR filter apparatus including a modulo integrator circuit configured to integrate input samples and to provide integrated input samples; and a polyphase FIR filter circuit configured to process the integrated input samples, the polyphase FIR filter circuit including a plurality of multiplier accumulator circuits, each configured to accumulate products of coefficients and respective integrated signal samples, wherein each of the multiplier accumulator circuits receives a subset of FIR filter coefficients, wherein the FIR filter coefficients are derived as the nth difference of original filter coefficients, where n is a number of integrators in the integrator circuit, and wherein the FIR filter circuit is configured to perform computation operations with modulo arithmetic.
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公开(公告)号：US20170294898A1
公开(公告)日：2017-10-12
申请号：US15632202
申请日：2017-06-23
Applicant: STMicroelectronics International N.V.
Inventor： Neha Bhargava , Ankur Bal
CPC classification number: H03H17/0283 , H03H17/0275 , H03H17/0664 , H03H17/0671 , H03H21/0027 , H03H2017/0245
Abstract: A polyphase decimation FIR filter apparatus including a modulo integrator circuit configured to integrate input samples and to provide integrated input samples; and a polyphase FIR filter circuit configured to process the integrated input samples, the polyphase FIR filter circuit including a plurality of multiplier accumulator circuits, each configured to accumulate products of coefficients and respective integrated signal samples, wherein each of the multiplier accumulator circuits receives a subset of FIR filter coefficients, wherein the FIR filter coefficients are derived as the nth difference of original filter coefficients, where n is a number of integrators in the integrator circuit, and wherein the FIR filter circuit is configured to perform computation operations with modulo arithmetic.
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