Low overhead mesochronous digital interface

    公开(公告)号:US12210373B2

    公开(公告)日:2025-01-28

    申请号:US18165855

    申请日:2023-02-07

    Abstract: An integrated circuit includes a first subsystem including a first clock generator configured to generate a first clock signal. The integrated circuit also includes a second subsystem including a second clock generator configured to generate a second clock signal. The first subsystem includes an edge detector configured to detect an edge of the second clock signal. The first clock generator generates the first clock signal with a selected phase relative to the second clock signal based on the edge of the second clock signal.

    Low latency filter
    5.
    发明授权
    Low latency filter 有权
    低延迟过滤器

    公开(公告)号:US08878710B2

    公开(公告)日:2014-11-04

    申请号:US13677674

    申请日:2012-11-15

    CPC classification number: H03M3/30 H03M3/344 H03M3/376 H03M3/462

    Abstract: In an embodiment, a set of input samples are filtered to provide a set of filtered samples using an N-tap filter. A steady-state-response-output sample of the N-tap filter is determined from a N/2th sample of the set of filtered samples.

    Abstract translation: 在一个实施例中,对一组输入样本进行滤波,以使用N抽头滤波器提供一组滤波样本。 N抽头滤波器的稳态响应输出样本由滤波样本集合的第N / 2个样本确定。

Patent Agency Ranking