公开(公告)号：US20190267380A1

公开(公告)日：2019-08-29

申请号：US15908575

申请日：2018-02-28

Applicant: STMICROELECTRONICS INTERNATIONAL N.V. ,  STMICROELECTRONICS S.R.L.

Inventor： Fabio DE SANTIS ,  Vikas RANA

IPC: H01L27/105 ,  H01L27/11521 ,  G11C29/00 ,  H01L27/112

Abstract: According to principles as discussed herein, an EEPROM cell is provided and then, after testing the code, using the exact same architecture, transistors, memory cells, and layout, the EEPROM cell is converted to a read-only memory (“ROM”) cell. This conversion is done on the very same integrated circuit die using the same layout, design, and timing with only a single change in an upper level mask in the memory array. In one embodiment, the mask change is the via mask connecting metal 1 to poly. This allows the flexibility to store the programming code as non-volatile memory code, and then after it has been tested, at time selected by the customer, some or all of that code from a code that can be written to a read-only code that is stored in a ROM cell that is composed the same transistors and having the same layout.

公开(公告)号：US20140112080A1

公开(公告)日：2014-04-24

申请号：US14061977

申请日：2013-10-24

Applicant: STMicroelectronics S.R.L.

Inventor： Marcella CARISSIMI ,  Marco PASOTTI ,  Fabio DE SANTIS

IPC: G11C7/06 ,  G11C7/08

CPC classification number: G11C7/22 ,  G11C7/06 ,  G11C7/062 ,  G11C7/08 ,  G11C7/10 ,  G11C16/0441 ,  G11C16/28

Abstract: An embodiment solution for operating a non-volatile memory of a complementary type is proposed. The non-volatile memory includes a plurality of sectors of memory cells, each memory cell being adapted to take a programmed state or an erased state. Moreover, the memory cells are arranged in locations each formed by a direct memory cell and a complementary memory cell. Each sector of the non-volatile memory is in a non-written condition when the corresponding memory cells are in equal states and is in a written condition wherein each location thereof stores a first logic value or a second logic value when the memory cells of the location are in a first combination of different states or in a second combination of different states, respectively. In an embodiment, a corresponding method includes the following steps: selecting at least one of the sectors, determining an indication of the number of memory cells in the programmed state and an indication of the number of memory cells in the erased state of the selected sector, and identifying the condition of the selected sector according to a comparison between the indication of the number of memory cells in the programmed state and the indication of the number of memory cells in the erased state.

Abstract translation: 提出了用于操作互补型非易失性存储器的实施例解决方案。 非易失性存储器包括存储器单元的多个扇区，每个存储器单元适于采取编程状态或擦除状态。 此外，存储单元被布置在由直接存储单元和互补存储单元形成的位置中。 当相应的存储器单元处于相同的状态并且处于写入状态时，非易失性存储器的每个扇区处于非写入状态，其中当其中的每个位置存储第一逻辑值或第二逻辑值时， 位置分别处于不同状态的第一组合或处于不同状态的第二组合中。 在一个实施例中，相应的方法包括以下步骤：选择扇区中的至少一个，确定编程状态下的存储器单元的数量的指示以及所选扇区的擦除状态中的存储器单元的数量的指示 并且根据编程状态下的存储单元的数量的指示与擦除状态下的存储单元的数量的指示之间的比较来识别所选扇区的状况。

公开(公告)号：US20200258885A1

公开(公告)日：2020-08-13

申请号：US16863856

申请日：2020-04-30

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics S.r.l.

Inventor： Fabio DE SANTIS ,  Vikas RANA

IPC: H01L27/105 ,  H01L27/11521 ,  H01L27/112 ,  G11C29/00 ,  H01L27/11519 ,  H01L27/11558

Abstract: According to principles as discussed herein, an EEPROM cell is provided and then, after testing the code, using the exact same architecture, transistors, memory cells, and layout, the EEPROM cell is converted to a read-only memory (“ROM”) cell. This conversion is done on the very same integrated circuit die using the same layout, design, and timing with only a single change in an upper level mask in the memory array. In one embodiment, the mask change is the via mask connecting metal 1 to poly. This allows the flexibility to store the programming code as non-volatile memory code, and then after it has been tested, at time selected by the customer, some or all of that code from a code that can be written to a read-only code that is stored in a ROM cell that is composed the same transistors and having the same layout.

公开(公告)号：US20150008939A1

公开(公告)日：2015-01-08

申请号：US14326263

申请日：2014-07-08

Applicant: STMicroelectronics S.r.l.

Inventor： Marco PASOTTI ,  Fabio DE SANTIS

IPC: G01R31/02

CPC classification number: G01R31/025 ,  G01R19/16571

Abstract: An embodiment of a measuring circuit for measuring the leakage current flowing in a portion of an electronic device when said portion is biased by a biasing unit of the electronic device is proposed. The measuring circuit includes a first section configured to generate a threshold current, a second section configured to receive the leakage current, a third section configured to compare the threshold current with the leakage current, and a fourth section configured to generate an output voltage based on the comparison between the threshold current and the leakage current. Said first section is configured to set the value of said threshold current to a different value at each reiteration of an operating cycle. Said fourth section is configured to measure said leakage current based on a detection of a change in the value of the output voltage between two reiterations of the operating cycle.

Abstract translation: 提出了一种测量电路的实施例，用于测量当电子设备的偏置单元偏压所述部分时在电子设备的一部分中流动的漏电流。 测量电路包括被配置为产生阈值电流的第一部分，被配置为接收泄漏电流的第二部分，被配置为将阈值电流与漏电流进行比较的第三部分，以及被配置为基于 阈值电流与漏电流的比较。 所述第一部分被配置为在操作周期的每次重复时将所述阈值电流的值设置为不同的值。 所述第四部分被配置为基于在操作周期的两次重复之间的输出电压的值的变化的检测来测量所述泄漏电流。

公开(公告)号：US20140036564A1

公开(公告)日：2014-02-06

申请号：US13954908

申请日：2013-07-30

Applicant: STMicroelectronics PVT LTD ,  STMicroelectronics S.r.l.

Inventor： Fabio DE SANTIS ,  Marco PASOTTI ,  Abhishek LAL

IPC: G11C5/02

CPC classification number: G11C5/02 ,  G11C5/025 ,  G11C7/18 ,  G11C8/12 ,  G11C16/00 ,  G11C16/08 ,  G11C16/24

Abstract: An embodiment of a non-volatile memory device includes: a memory array, having a plurality of non-volatile logic memory cells arranged in at least one logic row, the logic row including a first row and a second row sharing a common control line; and a plurality of bit lines. Each logic memory cell has a direct memory cell, for storing a logic value, and a complementary memory cell, for storing a second logic value, which is complementary to the first logic value in the corresponding direct memory cell. The direct memory cell and the complementary memory cell of each logic memory cell are coupled to respective separate bit lines and are placed one in the first row and the other in the second row of the respective logic row.

Abstract translation: 非易失性存储器件的实施例包括：存储器阵列，其具有布置在至少一个逻辑行中的多个非易失性逻辑存储器单元，所述逻辑行包括共享公共控制线的第一行和第二行; 和多个位线。 每个逻辑存储器单元具有用于存储逻辑值的直接存储单元和用于存储第二逻辑值的互补存储器单元，该第二逻辑值与对应的直接存储器单元中的第一逻辑值互补。 每个逻辑存储单元的直接存储单元和互补存储单元被耦合到相应的单独的位线，并且被放置在相应的逻辑行的第二行中的第一行而另一个中。