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公开(公告)号：US20230238055A1
公开(公告)日：2023-07-27
申请号：US17582675
申请日：2022-01-24
Inventor： Marco PASOTTI , Marcella CARISSIMI , Antonio GNUDI , Eleonora FRANCHI SCARSELLI , Alessio ANTOLINI , Andrea LICO
IPC: G11C11/4096 , G11C11/408 , G11C11/4094 , G11C11/4074 , G11C11/4076 , G06F7/544
CPC classification number: G11C11/4096 , G11C11/4085 , G11C11/4094 , G11C11/4074 , G11C11/4076 , G06F7/5443
Abstract: A circuit includes a memory array with memory cells arranged in a matrix of rows and columns, where each row includes a word line connected to the memory cells of the row, and each column includes a bit line connected to the memory cells of the column. Computational weights for an in-memory compute operation (IMCO) are stored in the memory cells. A word line control circuit simultaneously actuates word lines in response to input signals providing coefficient data for the IMCO by applying word line signal pulses. A column processing circuit connected to the bit lines processes analog signals developed on the bit lines in response to the simultaneous actuation of the word lines to generate multiply and accumulate output signals for the IMCO. Pulse widths of the signal pulses are modulated to compensate for cell drift. The IMCO further handles positive/negative calculation for the coefficient data and computational weights.
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2.发明申请ERROR CORRECTION IN DIFFERENTIAL MEMORY DEVICES WITH READING IN SINGLE-ENDED MODE IN ADDITION TO READING IN DIFFERENTIAL MODE 有权在具有读取单边模式的差异存储器件中的错误校正，以便在差异模式下读取公开(公告)号：US20150212880A1
公开(公告)日：2015-07-30
申请号：US14597824
申请日：2015-01-15
Applicant: STMICROELECTRONICS S.r.l.
Inventor： Marcella CARISSIMI , Marco PASOTTI
CPC classification number: G11C29/52 , G06F11/1048 , G11C7/18 , G11C11/5642 , G11C16/0441 , G11C16/26 , G11C16/28 , G11C2211/4013
Abstract: A differential memory device includes of memory locations having a direct memory cell and a complementary memory cell. A corresponding method includes receiving a request of reading a selected data word associated with a selected code word, reading a differential code word representing a differential version of the selected code word, verifying the differential code word according to an error correction code, setting the selected data word according to the differential code word in response to a positive verification. The method further includes reading at least one single-ended code word representing a single-ended version of the selected code word, verifying the single-ended code word according to the error correction code, and setting the selected data word according to the single-ended code word in response to a negative verification of the differential code word and to a positive verification of the single-ended code word.
Abstract translation: 差分存储器件包括具有直接存储单元和补充存储单元的存储单元。 相应的方法包括接收读取与所选码字相关联的所选数据字的请求，读取表示所选码字的差分版本的差分码字，根据纠错码验证差分码字，设置所选择的码字 数据字根据差分代码字响应积极的验证。 该方法还包括读取表示所选码字的单端版本的至少一个单端码字，根据纠错码验证单端码字，并根据单频码字单位设置所选择的数据字， 响应于对差分代码字的否定验证和对单端代码字的肯定验证，结束代码字。
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公开(公告)号：US20140036564A1
公开(公告)日：2014-02-06
申请号：US13954908
申请日：2013-07-30
Applicant: STMicroelectronics PVT LTD , STMicroelectronics S.r.l.
Inventor： Fabio DE SANTIS , Marco PASOTTI , Abhishek LAL
IPC: G11C5/02
CPC classification number: G11C5/02 , G11C5/025 , G11C7/18 , G11C8/12 , G11C16/00 , G11C16/08 , G11C16/24
Abstract: An embodiment of a non-volatile memory device includes: a memory array, having a plurality of non-volatile logic memory cells arranged in at least one logic row, the logic row including a first row and a second row sharing a common control line; and a plurality of bit lines. Each logic memory cell has a direct memory cell, for storing a logic value, and a complementary memory cell, for storing a second logic value, which is complementary to the first logic value in the corresponding direct memory cell. The direct memory cell and the complementary memory cell of each logic memory cell are coupled to respective separate bit lines and are placed one in the first row and the other in the second row of the respective logic row.
Abstract translation: 非易失性存储器件的实施例包括：存储器阵列，其具有布置在至少一个逻辑行中的多个非易失性逻辑存储器单元，所述逻辑行包括共享公共控制线的第一行和第二行; 和多个位线。 每个逻辑存储器单元具有用于存储逻辑值的直接存储单元和用于存储第二逻辑值的互补存储器单元，该第二逻辑值与对应的直接存储器单元中的第一逻辑值互补。 每个逻辑存储单元的直接存储单元和互补存储单元被耦合到相应的单独的位线，并且被放置在相应的逻辑行的第二行中的第一行而另一个中。
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4.发明公开公开(公告)号：US20240212751A1
公开(公告)日：2024-06-27
申请号：US18543847
申请日：2023-12-18
Applicant: STMicroelectronics S.r.l.
Inventor： Riccardo ZURLA , Marco PASOTTI , Marcella CARISSIMI , Alessandro CABRINI
CPC classification number: G11C13/004 , G06F17/16 , G11C13/0004 , G11C13/0028 , G11C13/003 , G11C2213/79
Abstract: A word line activation unit of an in-memory computation generates activation signals as a function of an input value. The in-memory computation device includes a memory array with a plurality of memory cells (each storing a computational weight) coupled to a bit line and each to a word line and a digital detector. A cell current flows through each memory cell as a function of the activation signal and the computational weight and a bit line current is generated as a function of a summation of the cell currents. The digital detector performs successive iterations on the bit line current. In each iteration: an integration stage generates an integration signal indicative of a time integral of the bit line current, and resets the integration signal when the integration signal reaches a threshold; and the counter stage updates the output signal in response to the integration signal reaching the threshold.
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公开(公告)号：US20230326524A1
公开(公告)日：2023-10-12
申请号：US17718908
申请日：2022-04-12
Inventor： Marco PASOTTI , Marcella CARISSIMI , Alessio ANTOLINI , Eleonora FRANCHI SCARSELLI , Antonio GNUDI , Andrea LICO , Paolo ROMELE
IPC: G11C13/00
CPC classification number: G11C13/0061 , G11C13/0004 , G11C13/0026 , G11C13/0038
Abstract: An in-memory computation (IMC) circuit includes a memory array formed by memory cells arranged in row-by-column matrix. Computational weights for an IMC operation are stored in the memory cells. Each column includes a bit line connected to the memory cells. A biasing circuit is connected between each bit line and a corresponding column output. A column combining circuit combines and integrates analog signals at the column outputs of the biasing circuits. Each biasing circuit operates to apply a fixed reference voltage level to its bit line. Each biasing circuit further includes a switching circuit that is controlled to turn on for a time duration controlled by asps comparison of a coefficient data signal to a ramp signal to generate the analog signal dependent on the computational weight. The ramp signal is generated using a reference current derived from a reference memory cell.
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Patent Agency Ranking
6.发明申请MEASURING LEAKAGE CURRENTS AND MEASURING CIRCUIT FOR CARRYING OUT SUCH MEASURING 有权测量泄漏电流和测量电路进行此类测量公开(公告)号：US20150008939A1
公开(公告)日：2015-01-08
申请号：US14326263
申请日：2014-07-08
Applicant: STMicroelectronics S.r.l.
Inventor： Marco PASOTTI , Fabio DE SANTIS
IPC: G01R31/02
CPC classification number: G01R31/025 , G01R19/16571
Abstract: An embodiment of a measuring circuit for measuring the leakage current flowing in a portion of an electronic device when said portion is biased by a biasing unit of the electronic device is proposed. The measuring circuit includes a first section configured to generate a threshold current, a second section configured to receive the leakage current, a third section configured to compare the threshold current with the leakage current, and a fourth section configured to generate an output voltage based on the comparison between the threshold current and the leakage current. Said first section is configured to set the value of said threshold current to a different value at each reiteration of an operating cycle. Said fourth section is configured to measure said leakage current based on a detection of a change in the value of the output voltage between two reiterations of the operating cycle.
Abstract translation: 提出了一种测量电路的实施例，用于测量当电子设备的偏置单元偏压所述部分时在电子设备的一部分中流动的漏电流。 测量电路包括被配置为产生阈值电流的第一部分，被配置为接收泄漏电流的第二部分，被配置为将阈值电流与漏电流进行比较的第三部分，以及被配置为基于 阈值电流与漏电流的比较。 所述第一部分被配置为在操作周期的每次重复时将所述阈值电流的值设置为不同的值。 所述第四部分被配置为基于在操作周期的两次重复之间的输出电压的值的变化的检测来测量所述泄漏电流。
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公开(公告)号：US20240212730A1
公开(公告)日：2024-06-27
申请号：US18542938
申请日：2023-12-18
Applicant: STMicroelectronics S.r.l.
Inventor： Marcella CARISSIMI , Marco PASOTTI , Riccardo ZURLA
Abstract: An in-memory computation device includes a word line activation circuit that receives an input signal indicative of input values and provides activation signals each as a function of the input value. The in-memory computation device further includes a memory array, a biasing circuit generating a bias voltage and a digital detector. The memory array has memory cells coupled to a bit line and each to a word line. Each memory cell stores a computational weight. In response to an activation signal, a cell current flows through each memory cell as a function of the bias voltage, the activation signal and the computational weight. A bit line current flows through the bit line as a function of a summation of the cell currents. The digital detector is coupled to the bit line, samples the bit line current and, in response, provides an output signal.
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公开(公告)号：US20230326499A1
公开(公告)日：2023-10-12
申请号：US17718755
申请日：2022-04-12
Inventor： Marco PASOTTI , Marcella CARISSIMI , Alessio ANTOLINI , Eleonora FRANCHI SCARSELLI , Antonio GNUDI , Andrea LICO
CPC classification number: G11C7/1063 , G11C7/12 , G11C8/08 , G11C7/14 , G11C7/16
Abstract: An in-memory computation (IMC) circuit includes a memory array formed by memory cells arranged in row-by-column matrix. Computational weights for an IMC operation are stored in the memory cells. Each column includes a bit line connected to the memory cells. A switching circuit is connected between each bit line and a corresponding column output. The switching circuit is controlled to turn on to generate the analog signal dependent on the computational weight and for a time duration controlled by the coefficient data signal. A column combining circuit combines (by addition and/or subtraction) and integrates analog signals at the column outputs of the biasing circuits. The addition/subtraction is dependent on one or more a sign of the coefficient data and a sign of the computational weight and may further implement a binary weighting function.
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9.发明申请公开(公告)号：US20220068400A1
公开(公告)日：2022-03-03
申请号：US17006510
申请日：2020-08-28
Inventor： Marco PASOTTI , Dario LIVORNESI , Roberto BREGOLI , Vikas RANA , Abhishek MITTAL
Abstract: An integrated circuit includes a memory array and a read voltage regulator that generates read voltages from the memory array. The read voltage regulator includes a replica memory cell and the replica bitline current path. The replica memory cell is a replica of memory cells of the memory array. The replica bitline current path is a replica of current paths associated with deadlines of the memory array. The read voltage regulator generates a read voltage based on the current passed through the replica bitline current path. This read voltage is then supplied to the wordlines of the memory array during a read operation.
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10.发明申请IDENTIFICATION OF A CONDITION OF A SECTOR OF MEMORY CELLS IN A NON-VOLATILE MEMORY 有权识别非易失性存储器中存储器细胞的一个条件的条件公开(公告)号：US20140112080A1
公开(公告)日：2014-04-24
申请号：US14061977
申请日：2013-10-24
Applicant: STMicroelectronics S.R.L.
Inventor： Marcella CARISSIMI , Marco PASOTTI , Fabio DE SANTIS
CPC classification number: G11C7/22 , G11C7/06 , G11C7/062 , G11C7/08 , G11C7/10 , G11C16/0441 , G11C16/28
Abstract: An embodiment solution for operating a non-volatile memory of a complementary type is proposed. The non-volatile memory includes a plurality of sectors of memory cells, each memory cell being adapted to take a programmed state or an erased state. Moreover, the memory cells are arranged in locations each formed by a direct memory cell and a complementary memory cell. Each sector of the non-volatile memory is in a non-written condition when the corresponding memory cells are in equal states and is in a written condition wherein each location thereof stores a first logic value or a second logic value when the memory cells of the location are in a first combination of different states or in a second combination of different states, respectively. In an embodiment, a corresponding method includes the following steps: selecting at least one of the sectors, determining an indication of the number of memory cells in the programmed state and an indication of the number of memory cells in the erased state of the selected sector, and identifying the condition of the selected sector according to a comparison between the indication of the number of memory cells in the programmed state and the indication of the number of memory cells in the erased state.
Abstract translation: 提出了用于操作互补型非易失性存储器的实施例解决方案。 非易失性存储器包括存储器单元的多个扇区，每个存储器单元适于采取编程状态或擦除状态。 此外，存储单元被布置在由直接存储单元和互补存储单元形成的位置中。 当相应的存储器单元处于相同的状态并且处于写入状态时，非易失性存储器的每个扇区处于非写入状态，其中当其中的每个位置存储第一逻辑值或第二逻辑值时， 位置分别处于不同状态的第一组合或处于不同状态的第二组合中。 在一个实施例中，相应的方法包括以下步骤：选择扇区中的至少一个，确定编程状态下的存储器单元的数量的指示以及所选扇区的擦除状态中的存储器单元的数量的指示 并且根据编程状态下的存储单元的数量的指示与擦除状态下的存储单元的数量的指示之间的比较来识别所选扇区的状况。
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