公开(公告)号：US20030027429A1

公开(公告)日：2003-02-06

申请号：US10189152

申请日：2002-07-02

Applicant: STMicroelectronics S.r.I.

Inventor： Enrico Bellandi ,  Francesco Pipia ,  Mauro Alessandri

IPC: H01L021/302 ,  H01L021/461

CPC classification number: H01L21/02071 ,  H01L21/02052 ,  H01L21/31116 ,  H01L21/76814

Abstract: The present invention relates to a process for removing post-etch residues or polymers from the surface of semiconductor devices which comprises treating the semiconductor device with an aqueous ammonia or ammonium hydroxide solution, optionally containing ozone for a time sufficient to effectively remove said post-etch residues or polymers from the surface of the semiconductor device and rinsing the semiconductor device with ozonized water, i.e. water enriched with ozone, in which water is preferably deionized (ozone-DIW).

Abstract translation: 本发明涉及用于从半导体器件表面去除蚀刻后残留物或聚合物的方法，该方法包括用氨水或氢氧化铵水溶液处理半导体器件，任选地含有臭氧足以有效去除所述后蚀刻 来自半导体器件表面的残留物或聚合物，并用臭氧化水（即，富含臭氧的水）漂洗半导体器件，其中水优选为去离子水（臭氧-DIW）。

公开(公告)号：US20030183869A1

公开(公告)日：2003-10-02

申请号：US10356351

申请日：2003-01-30

Applicant: STMicroelectronics S.r.I.

Inventor： Barbara Crivelli ,  Mauro Alessandri

IPC: H01L029/76

CPC classification number: H01L29/511 ,  H01L21/28273 ,  H01L21/3144

Abstract: A process manufactures an interpoly dielectric layer for non-volatile memory cells of a semiconductor device with an interpoly dielectric layer. The process begins with forming the tunnel oxide, and hence the amorphous or polycrystalline silicon layer, using conventional techniques. After the amorphous or polycrystalline silicon layer is surface cleansed and passivated, the surface of the polycrystalline layer is nitrided directly by using radical nitrogen. This is followed by the formation of the interpoly dielectric, either as an ONO layer or a single silicon layer, by means of the CVD technique. Masking to define the floating gate may be performed immediately before or after the direct nitridation step is carried out. The equivalent electrical thickness of the interpoly dielectric, obtained by combining the nitride oxide layer and by the following dielectric, does not exceed 130 Angstroms in either the ONO layer or the single silicon layer embodiment.

Abstract translation: 一种工艺制造用于具有多层电介质层的半导体器件的非易失性存储单元的互补电介质层。 该过程开始于使用常规技术形成隧道氧化物，因此形成非晶或多晶硅层。 在非晶或多晶硅层被表面清洁和钝化之后，多晶层的表面通过使用自由基氮直接氮化。 之后，通过CVD技术形成作为ONO层或单个硅层的互聚电介质。 可以在执行直接氮化步骤之前或之后立即执行用于限定浮动栅极的掩模。 通过组合氮氧化物层和随后的电介质获得的互聚电介质的等效电学厚度在ONO层或单硅层实施例中不超过130埃。