公开(公告)号：US20020097627A1

公开(公告)日：2002-07-25

申请号：US09960851

申请日：2001-09-21

Applicant: STMicroelectronics S.r.l.

Inventor： Andrea Sacco ,  Osama Khouri ,  Rino Micheloni ,  Guido Torelli

IPC: G11C005/00

CPC classification number: G11C16/08 ,  G11C5/147 ,  G11C8/08 ,  G11C8/10 ,  G11C8/14

Abstract: Described herein is a nonvolatile memory comprising a memory array organized according to global word lines and local word lines; a global row decoder; a local row decoder; a first supply stage for supplying the global row decoder; and a second supply stage for supplying the local row decoder; and a third supply stage for biasing the drain and source terminals of the memory cells of the memory array. Each of the supply stages comprises a respective resistive divider formed by a plurality of series-connected resistors, and a plurality of pass-gate CMOS switches each connected in parallel to a respective resistor. The nonvolatile memory further comprises a control circuit for controlling the pass-gate CMOS switches of the supply stages, and a switching circuit for selectively connecting the supply input of the control circuit to the output of the second supply stage during reading and programming of the memory, and to the output of the third supply stage during erasing of the memory.

Abstract translation: 这里描述的是一种非易失性存储器，包括根据全局字线和本地字线组织的存储器阵列; 全球排解码器; 一个本地行解码器; 用于提供全球行解码器的第一供应级; 以及用于提供本地行解码器的第二供应级; 以及用于偏置存储器阵列的存储单元的漏极和源极端子的第三供电级。 每个供电级包括由多个串联电阻器形成的相应电阻分压器，以及各自并联连接到相应电阻器的多个通栅CMOS开关。 非易失性存储器还包括用于控制供电级的通过栅极CMOS开关的控制电路和用于在存储器的读取和编程期间将控制电路的电源输入选择性地连接到第二电源级的输出的开关电路 并且在擦除存储器期间到达第三电源级的输出。