公开(公告)号：US20030107428A1

公开(公告)日：2003-06-12

申请号：US10290030

申请日：2002-11-07

Applicant: STMicroelectronics S.r.l.

Inventor： Osama Khouri ,  Andrea Pierin ,  Dario Soltesz ,  Guido Torelli

IPC: G05F003/02

CPC classification number: G11C5/145 ,  H02M3/073 ,  H02M2001/0032 ,  H02M2003/075 ,  H02M2003/077 ,  Y02B70/16

Abstract: A charge pump circuit, connected between a first voltage reference and an output terminal, comprises at least two stages comprising an elementary charge pump circuit connected between said first voltage reference and said output terminal, and adjustment circuitry connected between said output terminal and respective control terminals of said at least two stages. This circuitry is arranged to select for actuation an appropriate combination of these elementary stages according to the current absorbed from a load connected to the output terminal.

Abstract translation: 连接在第一参考电压和输出端子之间的电荷泵电路包括至少两个级，包括连接在所述第一参考电压和所述输出端子之间的基本电荷泵电路，以及连接在所述输出端子和相应控制端子之间的调节电路 的至少两个阶段。 该电路被设置为根据从连接到输出端子的负载吸收的电流来选择这些基本级的适当组合。

公开(公告)号：US20020097627A1

公开(公告)日：2002-07-25

申请号：US09960851

申请日：2001-09-21

Applicant: STMicroelectronics S.r.l.

Inventor： Andrea Sacco ,  Osama Khouri ,  Rino Micheloni ,  Guido Torelli

IPC: G11C005/00

CPC classification number: G11C16/08 ,  G11C5/147 ,  G11C8/08 ,  G11C8/10 ,  G11C8/14

Abstract: Described herein is a nonvolatile memory comprising a memory array organized according to global word lines and local word lines; a global row decoder; a local row decoder; a first supply stage for supplying the global row decoder; and a second supply stage for supplying the local row decoder; and a third supply stage for biasing the drain and source terminals of the memory cells of the memory array. Each of the supply stages comprises a respective resistive divider formed by a plurality of series-connected resistors, and a plurality of pass-gate CMOS switches each connected in parallel to a respective resistor. The nonvolatile memory further comprises a control circuit for controlling the pass-gate CMOS switches of the supply stages, and a switching circuit for selectively connecting the supply input of the control circuit to the output of the second supply stage during reading and programming of the memory, and to the output of the third supply stage during erasing of the memory.

Abstract translation: 这里描述的是一种非易失性存储器，包括根据全局字线和本地字线组织的存储器阵列; 全球排解码器; 一个本地行解码器; 用于提供全球行解码器的第一供应级; 以及用于提供本地行解码器的第二供应级; 以及用于偏置存储器阵列的存储单元的漏极和源极端子的第三供电级。 每个供电级包括由多个串联电阻器形成的相应电阻分压器，以及各自并联连接到相应电阻器的多个通栅CMOS开关。 非易失性存储器还包括用于控制供电级的通过栅极CMOS开关的控制电路和用于在存储器的读取和编程期间将控制电路的电源输入选择性地连接到第二电源级的输出的开关电路 并且在擦除存储器期间到达第三电源级的输出。

公开(公告)号：US20020196171A1

公开(公告)日：2002-12-26

申请号：US10060076

申请日：2002-01-29

Applicant: STMicroelectronics S.r.l.

Inventor： Rino Micheloni ,  Osama Khouri ,  Andrea Pierin ,  Stefano Gregori ,  Guido Torelli

IPC: H03M001/14

CPC classification number: G11C11/56 ,  G11C27/005 ,  H03M1/146 ,  H03M1/361

Abstract: An analog-to-digital conversion method and device for a multilevel non-volatile memory devicethat includes a multilevel memory cell. The method comprises a first step of converting the most significant bits contained in the memory cell, followed by a second step of converting the least significant bits. The first step is completed within a time interval corresponding to the rise transient of the gate voltage, and the second step is initiated at the end of the transient. Also disclosed is a scheme for error control coding in multilevel Flash memories. The n bits stored in a single memory cell are organized in different nullbit-layersnull, which are independent from one another. Error correction is carried out separately for each bit-layer. The correction of any failure in a single memory cell is achieved by using a simple error control code providing single-bit correction, regardless of the number of bits stored in a single cell.

Abstract translation: 用于多电平非易失性存储器设备的模数转换方法和装置包括多电平存储器单元。 该方法包括转换存储单元中包含的最高有效位的第一步骤，随后转换最低有效位的第二步骤。 在对应于栅极电压的上升瞬变的时间间隔内完成第一步，并且在瞬态结束时启动第二步。 还公开了一种用于多电平闪存中的错误控制编码的方案。 存储在单个存储器单元中的n位被组织在彼此独立的不同“位层”中。 针对每个位层分别执行错误校正。 通过使用提供单位校正的简单误差控制代码来实现单个存储器单元中的任何故障的校正，而不管存储在单个单元中的位数。

公开(公告)号：US20020157059A1

公开(公告)日：2002-10-24

申请号：US10015949

申请日：2001-11-02

Applicant: STMicroelectronics S.r.l.

Inventor： Stefano Gregori ,  Pietro Ferrari ,  Guido Torelli

IPC: H03M013/00

CPC classification number: H03M13/00 ,  G11C2211/5641

Abstract: Described herein is a method for constructing a multipurpose error-control code for multilevel memory cells operating with a variable number of storage levels, in particular for memory cells the storage levels of which can assume the values of the set nullba1, baaa2, . . . , ba1a2. . . ahnull, with b, a1, . . . , ah positive integers; the error-control code encoding information words, formed by k q-ary symbols, i.e., belonging to an alphabet containing q different symbols, with qnullnullba1, ba1a2, . . . , ba1a2ahnull, in corresponding code words formed by n q-ary symbols, with qnullba1a2ah, and having an error-correction capacity t, each code word being generated through an operation of multiplication between the corresponding information word and a generating matrix. The construction method comprises the steps of: acquiring the values of k, t, ba1, ba1a2, . . . , ba1a2. . .ah, which constitute the design specifications of said error-control code; calculating, as a function of qnullba1, k and t, the minimum value of n such that the Hamming limit is satisfied; calculating the maximum values {circumflex over (n)} and {circumflex over (k)} respectively of n and k that satisfy the Hamming limit for qnullba1, t and ({circumflex over (n)}-{circumflex over (k)})null(n-k); determining, as a function of t, the generating matrix of the abbreviated error-control code (n-k) on the finite-element field GF(ba1); constructing binary polynomial representations of the finite-element fields GF(ba1) GF(ba1a2), . . . , GF(ba1a2. . . ah); identifying, using the aforesaid exponential representations, the elements of the finite-element field GF(ba1a2ah), which are isomorphic to the elements of the finite-element fields GF(ba1), GF(ba1a2), . . . , GF(ba1a2. . . ah-1); establishing biunique correspondences between the elements of the finite-element fields GF(ba1), GF(ba1a2), . . . , GF(ba1a2. . . ah1) and the elements of the finite-element field GF(ba1a2ah) that are isomorphic to them; and replacing each of the elements of said generating matrix with the corresponding isomorphic element of the finite-element field GF(ba1a2. . . ah), thus obtaining a multipurpose generating matrix defining, together with the aforesaid biunique correspondences, a multipurpose error-control code that can be used with memory cells the storage levels of which can assume the values of the set nullba1, ba1a2, . . . , ba1a2. . . ahnullnull.

Abstract translation: 这里描述了一种用于构建以可变数量的存储级别操作的多级存储器单元的多用途错误控制代码的方法，特别是对于存储单元，其存储级别可以采用集合{ba1，baaa2，...， 。 。 ，ba1a2。 。 。 啊}，用b，a1，。 。 。 ，正整数; 由k个q元符号形成的错误控制码编码信息字，即属于包含q个不同符号的字母，与qepsi {ba1，ba1a2，... 。 。 ，ba1a2ah}，在具有q = ba1a2ah并且具有纠错能力t的由n个q元符号形成的相应码字中，每个码字通过相应信息字与生成矩阵之间的乘法运算而产生。 该构造方法包括以下步骤：获取k，t，ba1，ba1a2，...的值。 。 。 ，ba1a2。 。 .ah，构成设计

公开(公告)号：US20020099988A1

公开(公告)日：2002-07-25

申请号：US10003474

申请日：2001-10-25

Applicant: STMicroelectronics S.r.l.

Inventor： Khouri Osama ,  Stefano Gregori ,  Andrea Pierin ,  Rino Micheloni ,  Sergio Coronini ,  Guido Torelli

IPC: G11C029/00 ,  G06F007/02 ,  H03M013/00

CPC classification number: G11C27/005 ,  G11C7/062 ,  G11C11/5642 ,  G11C16/28 ,  G11C2207/063

Abstract: A circuit for reading a non-volatile memory cell has an output terminal for providing an output current, and a control terminal for receiving a voltage for controlling the output current. The reading circuit includes a feedback circuit which can be connected electrically to the output terminal and to the control terminal to generate the control voltage from a reference signal and from the output current. The feedback circuit also includes a current-amplification circuit having a first terminal for receiving a current-error signal derived from the reference signal and from the output current, and a second terminal for supplying an amplified current.