公开(公告)号：US10674578B1

公开(公告)日：2020-06-02

申请号：US16584059

申请日：2019-09-26

Applicant: STMicroelectronics S.r.l.

Inventor： Ignazio Cala′ ,  Salvatore Pantano ,  Santi Carlo Adamo

IPC: G06F3/00 ,  H05B45/10 ,  H03K3/42 ,  H05B47/18 ,  G06F9/30 ,  G06F9/38

Abstract: A circuit includes: a communication interface configured to receive data; a plurality of output terminals; a bank of input registers coupled to the communication interface; a bank of buffer registers; a bank of output registers; a signal generator configured to generate a plurality of output signals based on respective registers of the bank of output registers at respective output terminals; and a conversion stage configured to: when data is received by the bank of input registers from the communication interface, sequentially convert content of the input registers of the bank of input registers and store the converted content into corresponding buffer registers of the bank of buffer registers based on a conversion function, and when the conversion stage finishes storing the converted content into the buffer registers, simultaneously copy content from the buffer registers into corresponding output registers of the bank of output registers.

公开(公告)号：US10757779B2

公开(公告)日：2020-08-25

申请号：US16273661

申请日：2019-02-12

Applicant: STMicroelectronics S.r.l.

Inventor： Ignazio Cala′ ,  Santi Carlo Adamo

IPC: H05B33/08 ,  H05B45/37 ,  G06F13/42 ,  H03K7/08 ,  H05B45/10

Abstract: A circuit includes a set of LED driver devices and a controller including a set of nodes coupled to a first slave address pin and a second slave address pin in each LED driver devices in the set of LED driver devices. Each LED driver device includes: a finite state machine (FSM) configured to generate LED drive PWM-modulated signal patterns; an oscillator configured to generate a clock signal for the FSM; a first signal path activatable between the first slave address pin and the FSM; and a second signal path activatable between the FSM and the second slave address pin.