公开(公告)号：US20030224563A1

公开(公告)日：2003-12-04

申请号：US10323615

申请日：2002-12-18

Applicant: STMicroelectronics S.r.l.

Inventor： Mauro Alessandri ,  Barbara Crivelli ,  Romina Zonca

IPC: H01L021/336

CPC classification number: H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: A process for manufacturing a non-volatile memory cell having at least one gate region, the process including the steps of depositing a first dielectric layer onto a semiconductor substrate; depositing a first semiconductor layer onto the first dielectric layer to form a floating gate region of the memory cell; and defining the floating gate region of the memory cell in the first semiconductor layer. The process further includes the step of depositing a second dielectric layer onto the first conductive layer, the second dielectric layer having a higher dielectric constant than 10. Also disclosed is a memory cell integrated in a semiconductor substrate and having a gate region that has a dielectric layer formed over a first conductive layer and having a dielectric constant higher than 10.

Abstract translation: 一种用于制造具有至少一个栅极区域的非易失性存储单元的工艺，所述方法包括以下步骤：将第一介电层沉积到半导体衬底上; 在所述第一介电层上沉积第一半导体层以形成所述存储单元的浮动栅区; 以及限定第一半导体层中的存储单元的浮置栅极区。 该方法还包括在第一导电层上沉积第二电介质层的步骤，第二电介质层具有比10更高的介电常数。还公开了集成在半导体衬底中并具有栅极区的存储单元，该栅极区具有电介质 层形成在第一导电层上并具有高于10的介电常数。

公开(公告)号：US20020158285A1

公开(公告)日：2002-10-31

申请号：US10165010

申请日：2002-06-06

Applicant: STMicroelectronics S.r.l.

Inventor： Cesare Clementi ,  Gabriella Ghidini ,  Mauro Alessandri

IPC: H01L029/788

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/66825

Abstract: A process of fabricating a floating-gate memory device, the process including the steps of: forming a stack of superimposed layers including a floating gate region, a dielectric region, and a control gate region; and forming an insulating layer of oxynitride to the side of the floating gate region to completely seal the floating gate region outwards and improve the retention characteristics of the memory device. The insulating layer is formed during reoxidation of the sides of the floating gate region, after self-align etching the stack of layers and implanting the source/drain of the cell.