公开(公告)号：US20160284807A1

公开(公告)日：2016-09-29

申请号：US14930324

申请日：2015-11-02

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： David Petit ,  Frederic Monsieur ,  Xavier Federspiel ,  Gregory Bidal

IPC: H01L29/423 ,  H01L21/8234 ,  H01L29/10 ,  H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L29/42364 ,  H01L21/823412 ,  H01L21/823462 ,  H01L21/84 ,  H01L27/088 ,  H01L27/1203 ,  H01L27/127 ,  H01L29/0653 ,  H01L29/1033 ,  H01L29/7838

Abstract: A substrate of the silicon-on-insulator type is formed from an initial substrate of the silicon-on-insulator type having a semiconductor film on top of a buried insulating layer itself situated on top of a carrier substrate. A localized modification of a thickness of the semiconductor film is made so as to form a semiconductor film having different thicknesses in different regions.

Abstract translation: 绝缘体上硅型的衬底由绝缘体上硅型的初始衬底形成，其中半导体膜位于位于载体衬底顶部的掩埋绝缘层本身的顶部上。 制造半导体膜的厚度的局部修改以便形成在不同区域中具有不同厚度的半导体膜。

公开(公告)号：US20140075726A1

公开(公告)日：2014-03-20

申请号：US14084394

申请日：2013-11-19

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： David Petit ,  Sylvain Joblot ,  Pierre Bar ,  Jean-Francois Carpentier ,  Pierre Dautriche

IPC: H03H3/02

CPC classification number: H03H3/02 ,  G01N29/022 ,  G02F1/133707 ,  H03H3/04 ,  H03H9/0028 ,  H03H9/02102 ,  H03H9/175 ,  Y10T29/42 ,  Y10T29/49005 ,  Y10T29/49155

Abstract: A method for manufacturing a wafer on which are formed resonators, each resonator including, above a semiconductor substrate, a stack of layers including, in the following order from the substrate surface: a Bragg mirror; a compensation layer made of a material having a temperature coefficient of the acoustic velocity of a sign opposite to that of all the other stack layers; and a piezoelectric resonator, the method including the successive steps of: a) depositing the compensation layer; and b) decreasing thickness inequalities of the compensation layer due to the deposition method, so that this layer has a same thickness to within better than 2%, and preferably to within better than 1%, at the level of each resonator.

Abstract translation: 一种制造晶片的方法，其上形成有谐振器，每个谐振器包括在半导体衬底上方的一叠层，其从衬底表面依次包括：布拉格反射镜; 由具有与所有其它堆叠层相反的符号的声速的温度系数的材料制成的补偿层; 和压电谐振器，该方法包括以下连续步骤：a）沉积补偿层; 和b）由于沉积方法而减小补偿层的厚度不等式，使得该层在每个谐振器的电平上具有相同的厚度，优于2％以内，优选在1％以内。

公开(公告)号：US20130105893A1

公开(公告)日：2013-05-02

申请号：US13660681

申请日：2012-10-25

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： David Petit ,  Bruno Rauber

IPC: H01L27/088 ,  H01L21/336

CPC classification number: H01L29/7824 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/1095 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66689

Abstract: A DMOS on SOI transistor including an elongated gate extending across the entire width of an active area; a drain region of a first conductivity type extending across the entire width of the active area; a source region of the first conductivity type extending parallel to the gate and stopping before the limit of the active area at least on one side of the transistor width, an interval existing between the limit of the source region and the limit of the active area; a bulk region of a second conductivity type extending under the gate and in said interval; a more heavily-doped region of the second conductivity type extending on a portion of said interval on the side of the limit of the active area; and an elongated source metallization extending across the entire width of the active area.

Abstract translation: SOI晶体管上的DMOS，包括延伸跨有效区域的整个宽度的细长栅极; 在有源区的整个宽度上延伸的第一导电类型的漏区; 所述第一导电类型的源极区域平行于所述栅极延伸并且在所述有源区域的极限之前至少在所述晶体管宽度的一侧上停止，所述间隔存在于所述源极区域的极限与所述有源区域的极限之间; 在栅极和所述间隔内延伸的第二导电类型的主体区域; 所述第二导电类型的更高掺杂区域在所述间隔的所述有效面积极限侧的一部分上延伸; 以及延伸穿过有效区域的整个宽度的细长源金属化。

公开(公告)号：US09647625B2

公开(公告)日：2017-05-09

申请号：US14084394

申请日：2013-11-19

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： David Petit ,  Sylvain Joblot ,  Pierre Bar ,  Jean-Francois Carpentier ,  Pierre Dautriche

IPC: H03H3/02 ,  H03H9/02 ,  H03H3/04 ,  H03H9/00 ,  H03H9/17 ,  G02F1/1337 ,  G01N29/02

CPC classification number: H03H3/02 ,  G01N29/022 ,  G02F1/133707 ,  H03H3/04 ,  H03H9/0028 ,  H03H9/02102 ,  H03H9/175 ,  Y10T29/42 ,  Y10T29/49005 ,  Y10T29/49155

Abstract: A method for manufacturing a wafer on which are formed resonators, each resonator including, above a semiconductor substrate, a stack of layers including, in the following order from the substrate surface: a Bragg mirror; a compensation layer made of a material having a temperature coefficient of the acoustic velocity of a sign opposite to that of all the other stack layers; and a piezoelectric resonator, the method including the successive steps of: a) depositing the compensation layer; and b) decreasing thickness inequalities of the compensation layer due to the deposition method, so that this layer has a same thickness to within better than 2%, and preferably to within better than 1%, at the level of each resonator.