公开(公告)号：US09390786B2

公开(公告)日：2016-07-12

申请号：US14813278

申请日：2015-07-30

Applicant: STMicroelectronics SA ,  STMicroelectronics International N.V.

Inventor： Christophe Lecocq ,  Kaya Can Akyel ,  Amit Chhabra ,  Dibya Dipti

IPC: G11C11/34 ,  G11C11/417 ,  G11C11/412 ,  H01L27/11

CPC classification number: G11C11/417 ,  G11C11/412 ,  H01L27/1104

Abstract: An SRAM cell is formed of FDSOI-type NMOS and PMOS transistors. A doped well extends under the NMOS and PMOS transistors and is separated therefrom by an insulating layer. A bias voltage is applied to the doped well. The applied bias voltage is adjusted according to a state of the memory cell. For example, a temperature of the memory cell is sensed and the bias voltage adjusted as a function of the sensed temperature. The adjustment in the bias voltage is configured so that threshold voltages of the NMOS and PMOS transistors are substantially equal to n and p target threshold voltages, respectively.

Abstract translation: SRAM单元由FDSOI型NMOS和PMOS晶体管形成。 掺杂阱在NMOS和PMOS晶体管的下方延伸，并通过绝缘层与其分离。 偏置电压施加到掺杂阱。 施加的偏置电压根据存储单元的状态进行调整。 例如，感测存储器单元的温度，并根据检测到的温度调整偏置电压。 偏置电压的调整被配置为使得NMOS和PMOS晶体管的阈值电压分别基本上等于n和p个目标阈值电压。

公开(公告)号：US20240015945A1

公开(公告)日：2024-01-11

申请号：US18347435

申请日：2023-07-05

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics International N.V.

Inventor： Olivier Weber ,  Kedar Janardan Dhori ,  Promod Kumar ,  Shafquat Jahan Ahmed ,  Christophe Lecocq ,  Pascal Urard

IPC: H10B10/00 ,  G11C11/417

CPC classification number: H10B10/12 ,  H10B10/18 ,  G11C11/417

Abstract: In one embodiment, a semiconductor device includes a carrier substrate, a buried dielectric region overlying the carrier substrate, and a semiconductor film separated from the carrier substrate by the buried dielectric region. NMOS transistors and PMOS transistors are disposed at a surface of the semiconductor film and coupled together to form a static random access memory (SRAM) cell. The NMOS transistors and the PMOS transistors each include a gate dielectric layer having a thickness greater than three nanometers and an active region in the semiconductor film. The active region of the PMOS transistors are formed from a silicon-germanium alloy.

公开(公告)号：US20160049189A1

公开(公告)日：2016-02-18

申请号：US14813278

申请日：2015-07-30

Applicant: STMicroelectronics SA ,  STMicroelectronics International N.V.

Inventor： Christophe Lecocq ,  Kaya Can Akyel ,  Amit Chhabra ,  Dibya Dipti

IPC: G11C11/417

CPC classification number: G11C11/417 ,  G11C11/412 ,  H01L27/1104

Abstract: An SRAM cell is formed of FDSOI-type NMOS and PMOS transistors. A doped well extends under the NMOS and PMOS transistors and is separated therefrom by an insulating layer. A bias voltage is applied to the doped well. The applied bias voltage is adjusted according to a state of the memory cell. For example, a temperature of the memory cell is sensed and the bias voltage adjusted as a function of the sensed temperature. The adjustment in the bias voltage is configured so that threshold voltages of the NMOS and PMOS transistors are substantially equal to n and p target threshold voltages, respectively.

Abstract translation: SRAM单元由FDSOI型NMOS和PMOS晶体管形成。 掺杂阱在NMOS和PMOS晶体管的下方延伸，并通过绝缘层与其分离。 偏置电压施加到掺杂阱。 施加的偏置电压根据存储单元的状态进行调整。 例如，感测存储器单元的温度，并根据检测到的温度调整偏置电压。 偏置电压的调整被配置为使得NMOS和PMOS晶体管的阈值电压分别基本上等于n和p个目标阈值电压。

公开(公告)号：US12046324B2

公开(公告)日：2024-07-23

申请号：US17861458

申请日：2022-07-11

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics (Crolles 2) SAS

Inventor： Harsh Rawat ,  Praveen Kumar Verma ,  Promod Kumar ,  Christophe Lecocq

IPC: G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C8/08 ,  G11C8/10 ,  G11C11/00

CPC classification number: G11C8/10 ,  G11C7/1087 ,  G11C7/222 ,  G11C8/08

Abstract: A memory circuit includes an array of memory cells arranged with first word lines connected to a first sub-array storing less significant bits of data and second word lines connected to a second sub-array storing more significant bits of data. A row decoder circuit coupled to the first and second word lines generates word line signals. A word line gating circuit is configured to selectively gate passage of the word line signals to the second word lines for the second sub-array in response to assertion of a maximum value signal. A data modification circuit performs a mathematical operation on data read from the array of memory cells, and asserts the maximum value signal if the mathematical operation performed on the less significant bits of data from the first sub-array produces a maximum data value.