公开(公告)号：US09524992B2

公开(公告)日：2016-12-20

申请号：US14875320

申请日：2015-10-05

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Hye Young Ryu ,  Hee Jun Byeon ,  Woo Geun Lee ,  Kap Soo Yoon ,  Yoon Ho Kim ,  Chun Won Byun

IPC: G02F1/1362 ,  H01L27/12 ,  G02F1/1343 ,  G02F1/1368

CPC classification number: H01L27/127 ,  G02F1/134363 ,  G02F1/136227 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136222 ,  G02F2001/136295 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1262

Abstract: A thin film transistor array panel and a manufacturing method thereof according to an exemplary embodiment of the present invention form a contact hole in a second passivation layer formed of an organic insulator, protect a side of the contact hole by covering with a protection member formed of the same layer as the first field generating electrode and formed of a transparent conductive material, and etch the first passivation layer below the second passivation layer using the protection member as a mask. Therefore, it is possible to prevent the second passivation layer formed of an organic insulator from being overetched while etching the insulating layer below the second passivation layer so that the contact hole is prevented from being made excessively wide.

公开(公告)号：US09142680B2

公开(公告)日：2015-09-22

申请号：US13725333

申请日：2012-12-21

Applicant: Samsung Display Co., Ltd.

Inventor： Hye Young Ryu ,  Ki Won Kim ,  Jae Woo Park ,  Kap Soo Yoon ,  Young Joo Choi

IPC: H01L29/04 ,  H01L29/10 ,  H01L29/786 ,  H01L33/08 ,  H01L27/12

CPC classification number: H01L29/786 ,  H01L27/1225 ,  H01L27/124 ,  H01L33/08

Abstract: A thin film transistor array panel according to an exemplary embodiment of the present invention includes: a substrate; a gate line positioned on the substrate; a gate insulating layer positioned on the gate line; a semiconductor layer positioned on the gate insulating layer and having a channel portion; a data line including a source electrode and a drain electrode, the source and drain electrodes both positioned on the semiconductor layer; a passivation layer positioned on the data line and the drain electrode and having a contact hole formed therein; and a pixel electrode positioned on the passivation layer, wherein the pixel electrode contacts the drain electrode within the contact hole, and the channel portion of the semiconductor layer and the contact hole both overlap the gate line in a plan view of the substrate.

Abstract translation: 根据本发明的示例性实施例的薄膜晶体管阵列面板包括：基板; 位于基板上的栅极线; 位于栅极线上的栅极绝缘层; 位于所述栅极绝缘层上且具有沟道部分的半导体层; 包括源电极和漏电极的数据线，所述源极和漏极都位于所述半导体层上; 位于数据线和漏电极上并具有形成在其中的接触孔的钝化层; 位于所述钝化层上的像素电极，其中所述像素电极在所述接触孔内接触所述漏电极，并且所述半导体层的沟道部分和所述接触孔在所述衬底的平面图中与所述栅极线重叠。