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    GATE DRIVE CIRCUIT AND DISPLAY DEVICE HAVING THE GATE DRIVE CIRCUIT
    2.
    发明申请
    GATE DRIVE CIRCUIT AND DISPLAY DEVICE HAVING THE GATE DRIVE CIRCUIT 有权
    门控驱动电路和具有门控驱动电路的显示设备

    公开(公告)号：US20130335392A1

    公开(公告)日：2013-12-19

    申请号：US13719488

    申请日：2012-12-19

    Applicant: SAMSUNG DISPLAY CO., LTD.

    Inventor： DUC-HAN CHO ,  KANG-NAM KIM ,  JAE-HOON LEE ,  YOU-MEE HYUN ,  JONG-WOONG CHANG ,  YUN HEO

    IPC: H03K3/00 ,  G09G5/00

    CPC classification number: G06F3/038 ,  G09G3/3674 ,  G09G5/001 ,  G09G2310/0286 ,  G11C19/28 ,  H03K3/00

    Abstract: A gate drive circuit in which multiple stages are connected together one after each other. An n-th stage includes a pull-up part, a carry part, a pull-down part, a switching part, a first maintaining part and a second maintaining part. The pull-up part outputs a high voltage of a first clock signal. The carry part outputs a high voltage of the first clock signal. The pull-down part pulls-down the n-th gate signal into a first low voltage. The switching part outputs a first signal synchronized with the first clock signal during an interval other than a high voltage output interval of the n-th carry signal. The first maintaining part maintains the n-th gate signal at the first low voltage in response to the first signal. The second maintaining part maintains the n-th gate signal at the first low voltage in response to a second signal.

    Abstract translation: 一个栅极驱动电路，其中多个级彼此连接在一起。 第n级包括上拉部分，进位部分，下拉部分，切换部分，第一维持部分和第二维持部分。 上拉部分输出第一时钟信号的高电压。 进位部分输出第一时钟信号的高电压。 下拉部分将第n个门信号下拉到第一个低电压。 开关部分在与第n个进位信号的高电压输出间隔之外的间隔期间输出与第一时钟信号同步的第一信号。 第一维持部分响应于第一信号将第n个栅极信号保持在第一低电压。 第二维持部分响应于第二信号将第n个门信号保持在第一低电压。

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