公开(公告)号：US11592720B2

公开(公告)日：2023-02-28

申请号：US17829470

申请日：2022-06-01

Applicant: Samsung Display Co., Ltd.

Inventor： Si Hyun Ahn ,  Na Hyeon Cha ,  Sun Kwun Son

IPC: G02F1/1368 ,  G02F1/1343 ,  G02F1/1362

Abstract: A display device includes a first conductive layer including horizontal scan lines, and island-type electrodes, which are spaced apart from the horizontal scan lines; a first insulating layer disposed on the first conductive layer; a second conductive layer disposed on the first insulating layer, the second conductive layer including data lines, and a plurality of vertical scan lines; a second insulating layer disposed on the second conductive layer; and a third conductive layer disposed on the second insulating layer and including first shield electrodes, which cover first edges of the vertical scan lines, and second shield electrodes, which are spaced apart from the first shield electrodes, and cover second edges of the vertical scan lines, wherein the vertical scan lines are electrically connected to the island-type electrodes via contact holes that extend through the first insulating layer.

公开(公告)号：US11740519B2

公开(公告)日：2023-08-29

申请号：US17088166

申请日：2020-11-03

Applicant: Samsung Display Co., Ltd.

Inventor： Na Hyeon Cha ,  Si Hyun Ahn ,  Byoung Sun Na ,  Sun Kwun Son

IPC: G02F1/1362 ,  G02F1/1343 ,  G02F1/1368 ,  G09G3/36 ,  G09G3/00

CPC classification number: G02F1/136286 ,  G02F1/1368 ,  G02F1/134309 ,  G02F1/136213 ,  G09G3/006 ,  G09G3/3688 ,  G09G3/3696 ,  G02F2201/123 ,  G09G2300/0408

Abstract: The display device includes data lines, first gate lines arranged in parallel with the data lines, second gate lines intersecting the first gate lines, a line contact portion in which each of the plurality of first gate lines and each of the plurality of second gate lines are in contact with each other, a non-contact portion in which each of the plurality of first gate lines and each of the plurality of second gate lines are insulated from each other in an intersection area thereof, a first pixel including a first switching element connected to a corresponding second gate line among the second gate lines, and a second pixel including a second switching element connected to the second gate line connected to the first pixel, wherein magnitude of a first capacitance of the first switching element is different from magnitude of a first capacitance of the second switching element.

公开(公告)号：US09484466B2

公开(公告)日：2016-11-01

申请号：US14459949

申请日：2014-08-14

Applicant: Samsung Display Co., Ltd.

Inventor： Noboru Takeuchi ,  Kwi Hyun Kim ,  Seung Soo Baek ,  Si Hyun Ahn

IPC: H01L29/786

CPC classification number: H01L29/7869 ,  H01L29/78648 ,  H01L29/78696

Abstract: A thin film transistor includes: a gate electrode; a source electrode; a drain electrode facing the source electrode; an oxide semiconductor layer disposed between the gate electrode and the source electrode or between the gate electrode and the drain electrode; and a gate insulating layer disposed between the gate electrode and the source electrode or between the gate electrode and the drain electrode, wherein when a signal applied to the gate electrode is a turnoff signal, a voltage applied to the gate electrode has a negative value.

Abstract translation: 薄膜晶体管包括：栅电极; 源电极; 面向源电极的漏电极; 设置在所述栅电极和所述源电极之间或所述栅电极与所述漏电极之间的氧化物半导体层; 以及栅极绝缘层，其设置在所述栅极电极和所述源极电极之间，或者所述栅极电极与所述漏极电极之间，其中，当施加到所述栅电极的信号为截止信号时，施加到所述栅电极的电压为负值。

公开(公告)号：US11372301B2

公开(公告)日：2022-06-28

申请号：US17078024

申请日：2020-10-22

Applicant: Samsung Display Co., Ltd.

Inventor： Si Hyun Ahn ,  Na Hyeon Cha ,  Sun Kwun Son

IPC: G02F1/1368 ,  G02F1/1343 ,  G02F1/1362

Abstract: A display device includes a first conductive layer including horizontal scan lines, and island-type electrodes, which are spaced apart from the horizontal scan lines; a first insulating layer disposed on the first conductive layer; a second conductive layer disposed on the first insulating layer, the second conductive layer including data lines, and a plurality of vertical scan lines; a second insulating layer disposed on the second conductive layer; and a third conductive layer disposed on the second insulating layer and including first shield electrodes, which cover first edges of the vertical scan lines, and second shield electrodes, which are spaced apart from the first shield electrodes, and cover second edges of the vertical scan lines, wherein the vertical scan lines are electrically connected to the island-type electrodes via contact holes that extend through the first insulating layer.

公开(公告)号：US09490274B2

公开(公告)日：2016-11-08

申请号：US14700283

申请日：2015-04-30

Applicant: Samsung Display Co., Ltd.

Inventor： Hyung Jun Park ,  Kyung-Ho Park ,  Woo-Jung Shin ,  Si Hyun Ahn ,  Dong-Hyun Yoo

IPC: H01L27/12 ,  H01L29/417

CPC classification number: H01L27/124 ,  G02F1/136213 ,  G02F1/13624 ,  G02F2001/134345 ,  G02F2001/136245 ,  H01L29/41733 ,  H01L29/41758

Abstract: A thin film transistor array panel includes a first substrate; a gate line and a data line on the first substrate; a storage electrode line on the first substrate where a constant voltage is applied thereto; a first thin film transistor and a second thin film transistor which are connected to the gate line and the data line; a third thin film transistor which is connected to the gate line, the second thin film transistor and the storage electrode line; a first subpixel electrode which is connected to the first thin film transistor; and a second subpixel electrode which is connected to the second thin film transistor.

公开(公告)号：US20150236161A1

公开(公告)日：2015-08-20

申请号：US14459949

申请日：2014-08-14

Applicant: Samsung Display Co., Ltd.

Inventor： Noboru Takeuchi ,  Kwi Hyun Kim ,  Seung Soo Baek ,  Si Hyun Ahn

IPC: H01L29/786 ,  H01L23/00

CPC classification number: H01L29/7869 ,  H01L29/78648 ,  H01L29/78696

Abstract: A thin film transistor includes: a gate electrode; a source electrode; a drain electrode facing the source electrode; an oxide semiconductor layer disposed between the gate electrode and the source electrode or between the gate electrode and the drain electrode; and a gate insulating layer disposed between the gate electrode and the source electrode or between the gate electrode and the drain electrode, wherein when a signal applied to the gate electrode is a turnoff signal, a voltage applied to the gate electrode has a negative value.

Abstract translation: 薄膜晶体管包括：栅电极; 源电极; 面向源电极的漏电极; 设置在所述栅电极和所述源电极之间或所述栅电极与所述漏电极之间的氧化物半导体层; 以及栅极绝缘层，其设置在所述栅极电极和所述源极电极之间，或者所述栅极电极与所述漏极电极之间，其中，当施加到所述栅电极的信号为截止信号时，施加到所述栅电极的电压为负值。