公开(公告)号：US20180366530A1

公开(公告)日：2018-12-20

申请号：US15960111

申请日：2018-04-23

Applicant: Samsung Display Co., Ltd.

Inventor： Ilhun SEO ,  Yun-Mo CHUNG ,  Jae-Wook KANG ,  Hojin YOON ,  Daewoo LEE ,  Minseong YI ,  Tak-Young LEE ,  Miyeon CHO

IPC: H01L27/32

Abstract: A unit pixel includes a circuit structure, first and second wiring patterns, an interlayer insulating layer, a planarization layer, and a light emission structure. The first wiring pattern disposed on the circuit structure has a first bump structure. The interlayer insulating layer covers the circuit structure and the first wiring pattern. The second wiring pattern disposed on the interlayer insulating layer overlaps the first wiring pattern and has a second bump structure. The planarization layer covers the interlayer insulating layer and the second wiring pattern and includes a via-hole exposing at least a portion of be second wiring pattern. The light emission structure contacts the second wiring pattern through the via-hole. The first and second wiring patterns and the interlayer insulating layer form a capacitor, the light emission structure includes an OLED, and the capacitor is directly connected to an anode of the OLED.

公开(公告)号：US20200279904A1

公开(公告)日：2020-09-03

申请号：US16879661

申请日：2020-05-20

Applicant: Samsung Display Co., Ltd.

Inventor： Ilhun SEO ,  Yun-Mo CHUNG ,  Jae-Wook KANG ,  Hojin YOON ,  Daewoo LEE ,  Minseong YI ,  Tak-Young LEE ,  Miyeon CHO

IPC: H01L27/32 ,  H01L27/12

Abstract: A unit pixel includes a circuit structure, first and second wiring patterns, an interlayer insulating layer, a planarization layer, and a light emission structure. The first wiring pattern disposed on the circuit structure has a first bump structure. The interlayer insulating layer covers the circuit structure and the first wiring pattern. The second wiring pattern disposed on the interlayer insulating layer overlaps the first wiring pattern and has a second bump structure. The planarization layer covers the interlayer insulating layer and the second wiring pattern and includes a via-hole exposing at least a portion of the second wiring pattern. The light emission structure contacts the second wiring pattern through the via-hole. The first and second wiring patterns and the interlayer insulating layer form a capacitor, the light emission structure includes an OLED, and the capacitor is directly connected to an anode of the OLED.

公开(公告)号：US20230165092A1

公开(公告)日：2023-05-25

申请号：US18098069

申请日：2023-01-17

Applicant: Samsung Display Co., Ltd.

Inventor： Kang Moon JO ,  Sung Jae MOON ,  An Su LEE ,  Tak-Young LEE

IPC: H10K59/131 ,  H10K59/126 ,  H10K59/121

CPC classification number: H10K59/1315 ,  H10K59/126 ,  H10K59/1213 ,  H10K59/1216 ,  H01L27/1214

Abstract: A display device including: a substrate; first, second, and third data lines extending in a first direction on the substrate and disposed to be adjacent along a second direction crossing the first direction; a semiconductor layer disposed on the first, second, and third data lines; a first insulating layer disposed on the semiconductor layer; first, second, and third lower storage electrodes disposed on the first insulating layer and arranged to be adjacent along the first direction; a second insulating layer disposed on the first, second, and third lower storage electrodes; a first scan line extending in the second direction on the second insulating layer; a first pixel connected to the first scan line and the first data line; a second pixel connected to the first scan line and the second data line; and a third pixel connected to the first scan line and the third data line.

公开(公告)号：US20240112621A1

公开(公告)日：2024-04-04

申请号：US18213335

申请日：2023-06-23

Applicant: Samsung Display Co., LTD.

Inventor： Tak-Young LEE ,  Byungseok CHOI ,  Bogyeong KIM ,  Jonghee KIM ,  Boyong CHUNG

IPC: G09G3/32

CPC classification number: G09G3/32 ,  G09G2300/0426 ,  G09G2310/0202 ,  G09G2310/0291 ,  G09G2320/0233

Abstract: A display device includes a display panel including a plurality of pixels respectively connected to a plurality of data lines and a plurality of scan lines, a data driver which outputs data signals to the plurality of data lines including a first data line and a second data line branched from a data output terminal connected to the data driver, and a scan driver which outputs scan signals to the plurality of scan lines. A first scan output terminal and a second scan output terminal respectively connected to the plurality of scan lines are connected to the scan driver. One of the first scan output terminal and the second scan output terminal is connected to a resistance.

公开(公告)号：US20190334002A1

公开(公告)日：2019-10-31

申请号：US16273029

申请日：2019-02-11

Applicant: Samsung Display Co., Ltd.

Inventor： Ilhun SEO ,  Yun-Mo CHUNG ,  Daewoo LEE ,  Tak-Young LEE ,  Miyeon CHO

IPC: H01L29/417 ,  H01L27/32

Abstract: A thin film transistor substrate may include a base substrate, a semiconductor member, a gate electrode, a first insulation layer, and a source/drain electrode. The semiconductor member may overlap the base substrate. The gate electrode may overlap the semiconductor member and may be insulated from the semiconductor member. The first insulation layer may be positioned on the gate electrode and may include a first contact hole. The source/drain electrode may include a first discharge hole, may be electrically connected to the semiconductor member, and may be at least partially positioned inside the first contact hole. The first discharge hole may partially expose the semiconductor member.

公开(公告)号：US20150001523A1

公开(公告)日：2015-01-01

申请号：US14490725

申请日：2014-09-19

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Byoung-Keon PARK ,  Jong-Ryuk PARK ,  Yun-Mo CHUNG ,  Tak-Young LEE ,  Jin-Wook SEO ,  Ki-Yong LEE ,  Min-Jae JEONG ,  Yong-Duck SON ,  Byung-Soo SO ,  Seung-Kyu PARK ,  Dong-Hyun LEE ,  Kil-Won LEE ,  Jae-Wan Jung

IPC: H01L27/32 ,  H01L29/10 ,  H01L29/786

CPC classification number: H01L27/3244 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/02672 ,  H01L27/1277 ,  H01L27/3262 ,  H01L29/1033 ,  H01L29/66765 ,  H01L29/78609 ,  H01L29/78675 ,  H01L29/78678

Abstract: A method of forming a polycrystalline silicon layer includes forming a first amorphous silicon layer and forming a second amorphous silicon layer such that the first amorphous silicon layer and the second amorphous silicon layer have different film qualities from each other, and crystallizing the first amorphous silicon layer and the second amorphous silicon layer using a metal catalyst to form a first polycrystalline silicon layer and a second polycrystalline silicon layer. A thin film transistor includes the polycrystalline silicon layer formed by the method and an organic light emitting device includes the thin film transistor.

Abstract translation: 形成多晶硅层的方法包括：形成第一非晶硅层并形成第二非晶硅层，使得第一非晶硅层和第二非晶硅层彼此具有不同的膜质量，并使第一非晶硅层 以及使用金属催化剂形成第一多晶硅层和第二多晶硅层的第二非晶硅层。 薄膜晶体管包括通过该方法形成的多晶硅层和包括薄膜晶体管的有机发光器件。