公开(公告)号：US20240334673A1

公开(公告)日：2024-10-03

申请号：US18518687

申请日：2023-11-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Seok LEE ,  Hong Jun LEE ,  Hyun Geun CHOI ,  Keun Nam KIM ,  In Cheol NAM ,  Bo Won YOO ,  Jin Woo HAN

IPC: H10B12/00

CPC classification number: H10B12/038 ,  H10B12/482 ,  H10B12/488

Abstract: A semiconductor device includes a lower substrate, a memory cell structure including a wordline on the lower substrate, a bitline disposed on the lower substrate and intersecting the wordline, and a cell capacitor connected to the lower substrate, an upper substrate having a back side adjacent to the lower substrate and a front side opposite to the back side, a circuit element disposed on the front side of the upper substrate and overlapping the memory cell structure in a vertical direction, and a through via penetrating the upper substrate and electrically connecting the memory cell structure and the circuit element with each other.

公开(公告)号：US20240306404A1

公开(公告)日：2024-09-12

申请号：US18495519

申请日：2023-10-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun Geun CHOI ,  Ki Seok LEE ,  Keun Nam KIM ,  Seok Han PARK ,  Bo Won YOO ,  Jin Woo HAN

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H10B12/00

CPC classification number: H10B80/00 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H10B12/33 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06541 ,  H01L2924/1431 ,  H01L2924/1436

Abstract: A semiconductor memory device including an active pattern on a first substrate and comprising a first and second surfaces opposite to each other in a first direction, a data storage pattern between the active pattern and the first substrate and connected to a first surface of the active pattern, a bit line on the active pattern, connected to a second surface of the active pattern, and extending in a second direction, a word line on a sidewall of the active pattern, a second substrate, a peripheral gate structure on a first surface of the second substrate, a first connection wiring structure on the first surface of the second substrate and connected to the peripheral gate structure and bit line, a second connection wiring structure on a second surface of the second substrate and a through via penetrating the second substrate and connecting the first and second connection wiring structures.

公开(公告)号：US20240334682A1

公开(公告)日：2024-10-03

申请号：US18522932

申请日：2023-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bo Won YOO ,  Seok Han PARK ,  Ki Seok LEE ,  Hyun Geun CHOI ,  Jin Woo HAN

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/09 ,  H10B12/33 ,  H10B12/50

Abstract: A semiconductor memory device with improved integration and electrical characteristics. The semiconductor memory device includes a peri-gate structure, a first peri-connecting structure on the peri-gate structure, a data storage pattern on the first peri-connecting structure, an active pattern that includes a first surface and a second surface opposite to each other in a first direction, and a first side wall and a second side wall opposite to each other in a second direction, the first surface of the active pattern connected to the data storage pattern and facing a substrate, a bit line on the active pattern, connected to the second surface of the active pattern, and extends in the second direction, a word line on the first side wall of the active pattern and extending in a third direction, a second peri-connecting structure connected to the bit line and a connecting pad connected to the second peri-connecting wiring.

公开(公告)号：US20240315013A1

公开(公告)日：2024-09-19

申请号：US18406454

申请日：2024-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun Geun CHOI ,  Seok Han PARK ,  Bo Won YOO ,  Ki Seok LEE ,  Jin Woo HAN

IPC: H10B12/00 ,  H01L23/522 ,  H01L23/528

CPC classification number: H10B12/482 ,  H01L23/5226 ,  H01L23/5283 ,  H10B12/315 ,  H10B12/488 ,  H10B12/50

Abstract: A semiconductor memory device includes a peri-gate structure on a substrate, a first bonding pad on the peri-gate structure, a shielding conductive pattern on the first bonding pad, a second bonding pad between the shielding conductive pattern and the first bonding pad and contacting the first bonding pad, a bit line on the shielding conductive pattern extending in a first direction, an active pattern on the bit line and including a lower surface and an upper surface, and a first side wall and a second side wall opposite to each other in the first direction, the lower surface of the active pattern being connected to the bit line, a word line on the first side wall of the active pattern, and extends in a third direction, and a data storage pattern on the active pattern, and is connected to the upper surface of the active pattern.