公开(公告)号：US20240334673A1

公开(公告)日：2024-10-03

申请号：US18518687

申请日：2023-11-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Seok LEE ,  Hong Jun LEE ,  Hyun Geun CHOI ,  Keun Nam KIM ,  In Cheol NAM ,  Bo Won YOO ,  Jin Woo HAN

IPC: H10B12/00

CPC classification number: H10B12/038 ,  H10B12/482 ,  H10B12/488

Abstract: A semiconductor device includes a lower substrate, a memory cell structure including a wordline on the lower substrate, a bitline disposed on the lower substrate and intersecting the wordline, and a cell capacitor connected to the lower substrate, an upper substrate having a back side adjacent to the lower substrate and a front side opposite to the back side, a circuit element disposed on the front side of the upper substrate and overlapping the memory cell structure in a vertical direction, and a through via penetrating the upper substrate and electrically connecting the memory cell structure and the circuit element with each other.

公开(公告)号：US20210408004A1

公开(公告)日：2021-12-30

申请号：US17469340

申请日：2021-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Ho LEE ,  Eun A KIM ,  Ki Seok LEE ,  Jay-Bok CHOI ,  Keun Nam KIM ,  Yong Seok AHN ,  Jin-Hwan CHUN ,  Sang Yeon HAN ,  Sung Hee HAN ,  Seung Uk HAN ,  Yoo Sang HWANG

IPC: H01L27/108 ,  H01L23/528

Abstract: A semiconductor device includes a device isolation layer defining first and second active regions, a buried contact connected to the second active region, and first and second bit line structures disposed on the first and second active regions. Each of the first and second bit line structures comprises a bit line contact part and a bit line pass part. The bit line contact part is electrically connected to the first active region. The bit line pass part is disposed on the device isolation layer. A height of a lowest part of the buried contact is smaller than a height of a lowest part of the bit line pass part. The height of the lowest part of the buried contact is greater than a height of a lowest part of the bit line contact part. A lower end of the bit line pass part is buried in the second active region.

公开(公告)号：US20230371243A1

公开(公告)日：2023-11-16

申请号：US18101613

申请日：2023-01-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki Seok LEE ,  Keun Nam KIM ,  Seok Han PARK

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/05 ,  H10B12/315 ,  H10B12/488 ,  H10B12/50

Abstract: A semiconductor memory device includes a peripheral gate structure disposed on a substrate, a bit line disposed on the peripheral gate structure and extending in a first direction, a shielding structure disposed adjacent to the bit line on the peripheral gate structure and extending in the first direction, a first word line disposed on the bit line and the shielding structure and extending in a second direction, a second word line disposed on the bit line and the shielding structure, extending in the second direction, and spaced apart from the first word line in the first direction, first and second active patterns disposed on the bit line and disposed between the first and second word lines, and contact patterns connected to the first and second active patterns.

公开(公告)号：US20210257374A1

公开(公告)日：2021-08-19

申请号：US17035082

申请日：2020-09-28

Applicant: SAMSUNG ELECTRONICS co., LTD.

Inventor： KI SEOK LEE ,  Jae Hyun YOON ,  Kyu Jin KIM ,  Keun Nam KIM ,  Hui-Jung KIM ,  Kyu Hyun LEE ,  SANG-IL HAN ,  Sung Hee HAN ,  Yoo Sang HWANG

IPC: H01L27/108

Abstract: A includes an element isolation region, a first active region bounded by the element isolation region and that extends in a first direction and includes first and second parts disposed at a first level, and a third part disposed at a second level located above the first level, and a gate electrode disposed inside each of the element isolation region and the first active region and that extends in a second direction different from the first direction. The second part is spaced apart in the first direction from the first part, and the third part contacts each of the first and second parts. A first width in the second direction of the first part is less than a second width in the second direction of the third part.

公开(公告)号：US20240306404A1

公开(公告)日：2024-09-12

申请号：US18495519

申请日：2023-10-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun Geun CHOI ,  Ki Seok LEE ,  Keun Nam KIM ,  Seok Han PARK ,  Bo Won YOO ,  Jin Woo HAN

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H10B12/00

CPC classification number: H10B80/00 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H10B12/33 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06541 ,  H01L2924/1431 ,  H01L2924/1436

Abstract: A semiconductor memory device including an active pattern on a first substrate and comprising a first and second surfaces opposite to each other in a first direction, a data storage pattern between the active pattern and the first substrate and connected to a first surface of the active pattern, a bit line on the active pattern, connected to a second surface of the active pattern, and extending in a second direction, a word line on a sidewall of the active pattern, a second substrate, a peripheral gate structure on a first surface of the second substrate, a first connection wiring structure on the first surface of the second substrate and connected to the peripheral gate structure and bit line, a second connection wiring structure on a second surface of the second substrate and a through via penetrating the second substrate and connecting the first and second connection wiring structures.

公开(公告)号：US20210098460A1

公开(公告)日：2021-04-01

申请号：US16860276

申请日：2020-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Ho LEE ,  Eun A KIM ,  Ki Seok LEE ,  Jay-Bok CHOI ,  Keun Nam KIM ,  Yong Seok AHN ,  Jin-Hwan CHUN ,  Sang Yeon HAN ,  Sung Hee HAN ,  Seung Uk HAN ,  Yoo Sang HWANG

IPC: H01L27/108 ,  H01L23/528

Abstract: A semiconductor device includes a device isolation layer defining first and second active regions, a buried contact connected to the second active region, and first and second bit line structures disposed on the first and second active regions. Each of the first and second bit line structures comprises a bit line contact part and a bit line pass part. The bit line contact part is electrically connected to the first active region. The bit line pass part is disposed on the device isolation layer. A height of a lowest part of the buried contact is smaller than a height of a lowest part of the bit line pass part. The height of the lowest part of the buried contact is greater than a height of a lowest part of the bit line contact part. A lower end of the bit line pass part is buried in the second active region.