公开(公告)号：US11894092B2

公开(公告)日：2024-02-06

申请号：US17325690

申请日：2021-05-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myoungho Son ,  Wontaeck Jung ,  Buil Nam

IPC: G11C29/50 ,  H01L25/18 ,  H01L23/00 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/16 ,  G11C16/34 ,  H01L25/065 ,  H10B41/27 ,  H10B43/27

CPC classification number: G11C29/50004 ,  G11C11/5635 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/16 ,  G11C16/349 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H10B41/27 ,  H10B43/27 ,  G11C2029/5004 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A fail detecting method of a memory system including a nonvolatile memory device and a memory controller, the fail detecting method including: counting, by the memory controller, the number of erases of a word line connected to a pass transistor; issuing a first erase command, by the memory controller, when the number of erases reaches a reference value; applying a first voltage, by the nonvolatile memory device, in response to the first erase command, that causes a gate-source potential difference of the pass transistor to have a first value; detecting, by the memory controller, a leakage current in a word line, after the applying of the first voltage; and determining, by the memory controller, the word line as a fail when a leakage voltage caused by the leakage current is greater than a first threshold value.

公开(公告)号：US20250124995A1

公开(公告)日：2025-04-17

申请号：US18639033

申请日：2024-04-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Buil Nam ,  Jinsun Yeom

IPC: G11C29/12 ,  G11C29/40

Abstract: A nonvolatile memory device includes a memory cell array including a plurality of memory cells connected to a plurality of wordlines and a plurality of bitlines, a row decoder configured to select one of the plurality of wordlines in response to an address, and a wordline leakage current detector configured to determine whether the selected wordline is defective using trim information related to a level of a reference voltage or a gradient of a detect voltage during a test operation, wherein the trim information is stored internally in an electrical die sorting (EDS) process.

公开(公告)号：US11915773B2

公开(公告)日：2024-02-27

申请号：US17693571

申请日：2022-03-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghae Lee ,  Buil Nam ,  Jinsun Yeom ,  Sangwan Nam ,  Jaein Lee

IPC: G11C16/30 ,  G11C16/04 ,  G11C16/08 ,  G11C29/12 ,  G11C29/38

CPC classification number: G11C29/38 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/30 ,  G11C29/12005

Abstract: A nonvolatile memory device includes a memory cell array, a voltage generator, a voltage path circuit and a wordline defect detection circuit. The memory cell array includes memory cells and wordlines connected to the memory cells. The voltage generator generates a wordline voltage applied to the wordlines. The voltage path circuit between the voltage generator and the memory cell array transfers the wordline voltage to the wordlines. The wordline defect detection circuit is connected to a measurement node between the voltage generator and the voltage path circuit. The wordline defect detection circuit measures a path leakage current of the voltage path circuit based on a measurement voltage of the measurement node to generate an offset value corresponding to the path leakage current in a compensation mode and determines defect of each wordline of the wordlines based on the offset value and the measurement voltage in a defect detection mode.