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    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
    1.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20160163858A1

    公开(公告)日：2016-06-09

    申请号：US14956908

    申请日：2015-12-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dae-Won KIM ,  Jae-Kyu LEE

    IPC: H01L29/78 ,  H01L29/06 ,  H01L27/22 ,  H01L29/66

    CPC classification number: H01L29/7843 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/76232 ,  H01L27/228 ,  H01L29/0696 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/7813

    Abstract: A semiconductor device includes a substrate, first and second isolation layers, an insulation layer pattern, and a gate structure. The substrate has a cell region and a peripheral region. The first isolation layer is buried in a first upper portion of the substrate in the peripheral region. The second isolation layer is buried in a second upper portion of the substrate in the cell region, and extends along a first direction substantially parallel to a top surface of the substrate. The insulation layer pattern is buried in the first upper portion, and extends along a second direction substantially parallel to the top surface of the substrate and substantially perpendicular to the first direction. The insulation layer pattern has a lower surface higher than a lower surface of the second isolation layer, and applies a stress to a portion of the substrate adjacent thereto.

    Abstract translation: 半导体器件包括衬底，第一和第二隔离层，绝缘层图案和栅极结构。 衬底具有单元区域和周边区域。 第一隔离层埋设在周边区域中的基板的第一上部。 第二隔离层被埋在单元区域中的基板的第二上部，并且沿着基本上平行于基板的顶表面的第一方向延伸。 绝缘层图案被掩埋在第一上部中，并且沿着基本上平行于基板的顶表面并基本上垂直于第一方向的第二方向延伸。 绝缘层图案具有比第二隔离层的下表面更高的下表面，并且对与其相邻的基板的一部分施加应力。

    ACTIVE STRUCTURES OF A SEMICONDUCTOR DEVICE AND METHODS OF MANUFACTURING THE SAME
    2.
    发明申请
    ACTIVE STRUCTURES OF A SEMICONDUCTOR DEVICE AND METHODS OF MANUFACTURING THE SAME 有权
    半导体器件的主动结构及其制造方法

    公开(公告)号：US20160163543A1

    公开(公告)日：2016-06-09

    申请号：US14955193

    申请日：2015-12-01

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Dae-Won KIM ,  Jae-Kyu LEE

    IPC: H01L21/02

    CPC classification number: H01L21/762 ,  H01L21/3083 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10823 ,  H01L27/2436 ,  H01L27/2463 ,  H01L29/4236 ,  H01L29/78 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

    Abstract: A method of forming patterns of a semiconductor device, including partially etching an upper portion of a substrate to form first preliminary active patterns and a first trench, each of the first preliminary active patterns having a first width, and the first trench having a second width of about 2 to 3 times the first width; forming an insulating spacer on each sidewall of the first trench to form a second trench having the first width; forming a second preliminary active pattern in the second trench, the second preliminary active pattern having the first width; partially etching the first and second preliminary active patterns to form a plurality of first active patterns and a plurality of second active patterns and an opening between the plurality of first and second active patterns; and forming an insulation pattern to fill the opening.

    Abstract translation: 一种形成半导体器件的图案的方法，包括部分蚀刻衬底的上部以形成第一预活性图案和第一沟槽，每个第一预活性图案具有第一宽度，并且第一沟槽具有第二宽度 约为第一宽度的2〜3倍; 在所述第一沟槽的每个侧壁上形成绝缘垫片以形成具有所述第一宽度的第二沟槽; 在所述第二沟槽中形成第二预活性图案，所述第二预活性图案具有所述第一宽度; 部分地蚀刻第一和第二预活性图案以形成多个第一有源图案和多个第二有源图案以及多个第一和第二活动图案之间的开口; 并形成绝缘图案以填充开口。

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