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公开(公告)号：US11863188B2
公开(公告)日：2024-01-02
申请号：US17843585
申请日：2022-06-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Byounggon Kang , Dalhee Lee
CPC classification number: H03K3/0372 , H03K19/20
Abstract: A flip-flop circuit includes a first master latch circuit transmitting an inverted signal of an input signal received from an external device to a first node and transmitting an inverted signal of a signal of the first node to a second node, according to a first control signal having a first logic level or a second control signal having a second logic level, a first slave latch circuit transmitting an inverted signal of a signal of the second node to a third node according to the first control signal having the second logic level or the second control signal having the first logic level, a first output inverter generating a first output signal by inverting a signal of the third node, and a first control signal generation circuit generating the first control signal and the second control signal based on a clock signal and the signal of the first node.
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公开(公告)号：US11336269B2
公开(公告)日：2022-05-17
申请号：US16886187
申请日：2020-05-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dalhee Lee , Byounggon Kang
Abstract: An integrated circuit may include a clock gating cell based. The clock gating cell may include a first 2-input logic gate configured to receive a clock input and a first signal and generate a second signal, an inverter configured to receive the second signal and generate a clock output, and a 3-input logic gate including a second 2-input logic gate configured to generate the first signal. The first 2-input logic gate and the second 2-input logic gate form a set reset (SR) latch by being cross-coupled, the 3-input logic gate includes a feedback transistor configured to exclusively receive an internal signal of the first 2-input logic gate, and an activation of the feedback transistor by the internal signal is configured to avoid a race condition by preventing a pull-up or a pull-down of a first node at which the first signal is generated.
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公开(公告)号：US10411677B2
公开(公告)日：2019-09-10
申请号：US15649776
申请日：2017-07-14
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Ha-Young Kim , Dalhee Lee , Hyoung-Suk Oh , Keunho Lee , Taejoong Song , Sungwe Cho
IPC: H03K3/356 , H03K23/00 , H03K3/3562
Abstract: A flip-flop includes an input interface, a first latch, a third inverter, and a second latch. The third inverter and the fifth inverter include first transistors of a first type formed between a first power contact and a second power contact supplied with a power supply voltage on first-type fins, and second transistors of a second type formed between a first ground contact and a second ground contact supplied with a ground voltage on second-type fins.
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4.发明公开公开(公告)号：US20240235533A9
公开(公告)日：2024-07-11
申请号：US18373017
申请日：2023-09-26
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Byounggon Kang , Dalhee Lee
Abstract: A clock gating cell is provided. The clock gating cell includes: an inverter circuit configured to generate an inverted clock signal by inverting a clock signal; a first control circuit configured to receive the inverted clock signal, an enable signal, and a scan enable signal, and output a first internal signal at a first node; a second control circuit configured to receive the first internal signal, the clock signal, the enable signal, and the scan enable signal, and output a second internal signal at a second node; and an output driver configured to receive the second internal signal, and output an output clock signal to an output node and a third internal signal to a third node. The first control circuit and the second control circuit are configured to receive the third internal signal at the third node.
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公开(公告)号：US10749527B2
公开(公告)日：2020-08-18
申请号：US16056072
申请日：2018-08-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dalhee Lee , Jintae Kim , Jaeha Lee
IPC: H03K19/0175 , H03K19/0185
Abstract: A level shifting circuit includes a level shifting portion configured to receive an input signal and generate an output signal, and a current adjustment circuit connected between the level shifting portion and a drive high voltage node at which a drive high voltage is applied. The current adjustment circuit is configured to adjust an amount of current provided from the drive high voltage node to the level shifting portion.
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Patent Agency Ranking
公开(公告)号：US10720909B2
公开(公告)日：2020-07-21
申请号：US16522835
申请日：2019-07-26
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Ha-Young Kim , Dalhee Lee , Hyoung-Suk Oh , Keunho Lee , Taejoong Song , Sungwe Cho
IPC: H03K3/356 , H03K3/3562 , H03K23/00
Abstract: A flip-flop includes an input interface, a first latch, a third inverter, and a second latch. The third inverter and the fifth inverter include first transistors of a first type formed between a first power contact and a second power contact supplied with a power supply voltage on first-type fins, and second transistors of a second type formed between a first ground contact and a second ground contact supplied with a ground voltage on second-type fins.
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公开(公告)号：US12044733B2
公开(公告)日：2024-07-23
申请号：US18194643
申请日：2023-04-02
Applicant: Samsung Electronics Co., Ltd.
Inventor： Byounggon Kang , Dalhee Lee , Giyoung Yang , Minji Kim , Taejung Seol , Jaebeom Yang
IPC: G01R31/3185 , G01R31/317
CPC classification number: G01R31/318525 , G01R31/31725 , G01R31/318541
Abstract: A flip-flop circuit may include a selection circuit, a master latch circuit and a slave latch circuit. The selection circuit includes a multiplexer and first and second inverters. The multiplexer outputs a data signal or a scan input signal to a first node in response to an enable signal. The first inverter is connected to the first node and provides an inversion of a signal of the first node to a second node in response to a clock signal. The second inverter is connected to the second node and provides an inversion of the signal of the second node to a third node in response to the clock signal and a signal of a fourth node. The master latch circuit is connected between the third and fourth nodes. The slave latch circuit is connected between the fourth node and an output terminal of the flip-flop circuit.
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8.发明公开公开(公告)号：US20240137012A1
公开(公告)日：2024-04-25
申请号：US18373017
申请日：2023-09-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Byounggon Kang , Dalhee Lee
Abstract: A clock gating cell is provided. The clock gating cell includes: an inverter circuit configured to generate an inverted clock signal by inverting a clock signal; a first control circuit configured to receive the inverted clock signal, an enable signal, and a scan enable signal, and output a first internal signal at a first node; a second control circuit configured to receive the first internal signal, the clock signal, the enable signal, and the scan enable signal, and output a second internal signal at a second node; and an output driver configured to receive the second internal signal, and output an output clock signal to an output node and a third internal signal to a third node. The first control circuit and the second control circuit are configured to receive the third internal signal at the third node.
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公开(公告)号：US20170117898A1
公开(公告)日：2017-04-27
申请号：US15285348
申请日：2016-10-04
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dalhee Lee , Jintae Kim , Jaeha Lee
IPC: H03K19/0185
CPC classification number: H03K19/018521
Abstract: A level shifting circuit includes a level shifting portion configured to receive an input signal and generate an output signal, and a current adjustment circuit connected between the level shifting portion and a drive high voltage node at which a drive high voltage is applied. The current adjustment circuit is configured to adjust an amount of current provided from the drive high voltage node to the level shifting portion.
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公开(公告)号：US20240061039A1
公开(公告)日：2024-02-22
申请号：US18194643
申请日：2023-04-02
Applicant: Samsung Electronics Co., Ltd.
Inventor： Byounggon Kang , Dalhee Lee , Giyoung Yang , Minji Kim , Taejung Seol , Jaebeom Yang
IPC: G01R31/3185 , G01R31/317
CPC classification number: G01R31/318525 , G01R31/318541 , G01R31/31725
Abstract: A flip-flop circuit may include a selection circuit, a master latch circuit and a slave latch circuit. The selection circuit includes a multiplexer and first and second inverters. The multiplexer outputs a data signal or a scan input signal to a first node in response to an enable signal. The first inverter is connected to the first node and provides an inversion of a signal of the first node to a second node in response to a clock signal. The second inverter is connected to the second node and provides an inversion of the signal of the second node to a third node in response to the clock signal and a signal of a fourth node. The master latch circuit is connected between the third and fourth nodes. The slave latch circuit is connected between the fourth node and an output terminal of the flip-flop circuit.
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