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28 条记录 (耗时 0.019 秒)

    System on chip
    2.
    发明授权
    System on chip 有权
    片上系统

    公开(公告)号：US09589955B2

    公开(公告)日：2017-03-07

    申请号：US14872774

    申请日：2015-10-01

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Sang-Hoon Baek ,  Sun-Young Park ,  Sang-Kyu Oh ,  Ha-Young Kim ,  Jung-Ho Do ,  Moo-Gyu Bae ,  Seung-Young Lee

    IPC分类号： H01L23/48 ,  H01L29/40 ,  H01L27/088 ,  H01L27/02 ,  H01L27/11

    CPC分类号： H01L27/088 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/1104

    摘要： Systems on chips are provided. A system on chip (SoC) includes a first gate line, a second gate line and a third gate line extending in a first direction, a gate isolation region cutting the first gate line, the second gate line and the third gate line and extending in a second direction across the first direction, a first gate contact formed on the second gate line arranged between the first gate line and the third gate line, and electrically connecting the cut second gate line, a second gate contact formed on the first gate line, a third gate contact formed on the third gate line, a first metal line electrically connecting the second gate contact and the third gate contact, and a second metal line electrically connected to the first gate contact.

    摘要翻译： 提供芯片系统。 片上系统（SoC）包括第一栅极线，第二栅极线和沿第一方向延伸的第三栅极线，栅极隔离区域切割第一栅极线，第二栅极线和第三栅极线并且在 在第一方向上的第二方向，形成在第二栅极线上的第一栅极接触，布置在第一栅极线和第三栅极线之间，并且电连接切割的第二栅极线，形成在第一栅极线上的第二栅极接触， 形成在第三栅极线上的第三栅极触点，电连接第二栅极触点和第三栅极触点的第一金属线以及电连接到第一栅极触点的第二金属线。

    Semiconductor device
    3.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11387255B2

    公开(公告)日：2022-07-12

    申请号：US16989160

    申请日：2020-08-10

    申请人： Samsung Electronics Co., Ltd.

    发明人： Jintae Kim ,  Ha-Young Kim ,  Sinwoo Kim ,  Moo-Gyu Bae ,  Jaeha Lee

    IPC分类号： H01L27/11597 ,  H01L27/108 ,  H01L27/11524 ,  H01L27/06

    摘要： Disclosed is a semiconductor device comprising a logic cell that is on a substrate and includes first and second active regions spaced apart from each other in a first direction, first and second active patterns that are respectively on the first and second active regions and extend in a second direction intersecting the first direction, gate electrodes extending in the first direction and running across the first and second active patterns, first connection lines that are in a first interlayer dielectric layer on the gate electrodes and extend parallel to each other in the second direction, and second connection lines that are in a second interlayer dielectric layer on the first interlayer dielectric layer and extend parallel to each other in the first direction.

    Semiconductor device including standard cell
    4.
    发明授权
    Semiconductor device including standard cell 有权

    公开(公告)号：US11355489B2

    公开(公告)日：2022-06-07

    申请号：US17009941

    申请日：2020-09-02

    申请人： Samsung Electronics Co., Ltd.

    发明人： Byounggon Kang ,  Subin Jin ,  Ha-Young Kim

    IPC分类号： H01L27/02 ,  H03K3/3562 ,  H03K3/037 ,  H01L27/118

    摘要： A semiconductor device includes a standard cell, which includes first to fourth active areas that are extended in a first direction, first to fourth gate lines that are extended in a second direction perpendicular to the first direction over the first to fourth active areas and are disposed parallel to each other, a first cutting layer that is disposed between the first active area and the second active area and separates the second and third gate lines, a second cutting layer that is disposed between the third active area and the fourth active area and separates the second and third gate lines, a first gate contact that is formed on the second gate line separated by the first cutting layer and the second cutting layer, and a second gate contact that is formed on the third gate line separated by the first cutting layer and the second cutting layer.

    System on chip
    5.
    发明授权
    System on chip 有权

    公开(公告)号：US10541237B2

    公开(公告)日：2020-01-21

    申请号：US16037581

    申请日：2018-07-17

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Sang-Hoon Baek ,  Sun-Young Park ,  Sang-Kyu Oh ,  Ha-Young Kim ,  Jung-Ho Do ,  Moo-Gyu Bae ,  Seung-Young Lee

    IPC分类号： H01L23/48 ,  H01L29/40 ,  H01L27/088 ,  H01L27/02 ,  H01L27/11 ,  H01L21/8234 ,  H01L23/528

    摘要： A method is provided. The method includes forming a first to third gate lines on a substrate, the second gate line formed between the first and third gate lines; forming a gate isolation region to cut the first to third gate lines into two first sub gate lines, two second sub gate lines and two third sub gate lines, respectively; forming a first gate contact on one of the two first sub gate lines; forming a second gate contact on the two second sub gate lines; forming a third gate contact on one of the two third sub gate lines; forming a first metal line to connect the first and third gate contacts; and forming a second metal line. The first to third gate lines extend in a first direction, and the gate isolation region extends in a second direction different from the first direction.

    Semiconductor device
    7.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11699992B2

    公开(公告)日：2023-07-11

    申请号：US16726379

    申请日：2019-12-24

    申请人： Samsung Electronics Co., Ltd.

    发明人： Jintae Kim ,  Byounggon Kang ,  Changbeom Kim ,  Ha-Young Kim ,  Yongeun Cho

    IPC分类号： H03K3/037 ,  H01L27/02 ,  H01L23/528 ,  H01L29/06 ,  H01L27/092 ,  H01L23/522 ,  H01L29/423

    CPC分类号： H03K3/0372 ,  H01L23/5226 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/42392

    摘要： A semiconductor device includes a flip flop cell. The flip flop cell is formed on a semiconductor substrate, includes a flip flop circuit, and comprises a scan mux circuit, a master latch circuit, a slave latch circuit, a clock driver circuit, and an output circuit. Each of the scan mux circuit, the master latch circuit, the slave latch circuit, the clock driver circuit, and the output circuit includes a plurality of active devices which together output a resulting signal for that circuit based on inputs, is a sub-circuit of the flip flop circuit, and occupies a continuously-bounded area of the flip flop circuit from a plan view. At least a first sub-circuit and a second sub-circuit of the sub-circuits overlap from the plan view in a first overlap region, the first overlap region including part of a first continuously-bounded area for the first sub-circuit and part of a second continuously-bounded area for the second sub-circuit.

    Semiconductor device
    8.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11387229B2

    公开(公告)日：2022-07-12

    申请号：US16826756

    申请日：2020-03-23

    申请人： Samsung Electronics Co., Ltd.

    发明人： Jaeha Lee ,  Ha-Young Kim ,  Bonghyun Lee ,  Soyoung Lee ,  Yongeun Cho

    IPC分类号： H01L29/76 ,  H01L27/02 ,  G06F30/398 ,  G06F30/394 ,  G06F30/392

    摘要： Disclosed is a semiconductor device comprising a logic cell including first and second active regions spaced apart in a first direction on a substrate, first and second active patterns on the first and second active regions and extend in a second direction, first and second source/drain patterns on the first and second active patterns, gate electrodes extending in the first direction to run across the first and second active patterns and arranged in the second direction at a first pitch, first lines in a first interlayer dielectric layer on the gate electrodes and each electrically connected to the first source/drain pattern, the second source/drain pattern, or the gate electrode, and second lines in a second interlayer dielectric layer on the first interlayer dielectric layer and extending parallel to each other in the first direction.

    Integrated circuit and method of designing integrated circuit
    9.
    发明授权
    Integrated circuit and method of designing integrated circuit 有权

    公开(公告)号：US10216883B2

    公开(公告)日：2019-02-26

    申请号：US15351545

    申请日：2016-11-15

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Ha-Young Kim ,  Sung-We Cho ,  Tae-Joong Song

    IPC分类号： G06F17/50 ,  G03F1/00 ,  G03F7/00 ,  G03F7/20

    摘要： A computer-implemented method of designing an integrated circuit (IC) includes allocating a plurality of colors to a plurality of patterns corresponding to one layer of a first cell so that a multi-patterning technology is designated for use in forming the plurality of patterns, the first cell being a multi-height cell corresponding to a plurality of rows, generating a plurality of shift cells, in which a color remapping operation associated with the plurality of patterns is performed for each row, with respect to the first cell, and storing a cell set including the first cell and the plurality of shift cells in a standard cell library.

    System on chip
    10.
    发明授权
    System on chip 有权

    公开(公告)号：US10050032B2

    公开(公告)日：2018-08-14

    申请号：US15416016

    申请日：2017-01-26

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Sang-Hoon Baek ,  Sun-Young Park ,  Sang-Kyu Oh ,  Ha-Young Kim ,  Jung-Ho Do ,  Moo-Gyu Bae ,  Seung-Young Lee

    IPC分类号： H01L23/48 ,  H01L29/40 ,  H01L27/088 ,  H01L23/528 ,  H01L27/02 ,  H01L27/11 ,  H01L21/8234

    摘要： Systems on chips are provided. A system on chip (SoC) includes a first gate line, a second gate line and a third gate line extending in a first direction, a gate isolation region cutting the first gate line, the second gate line and the third gate line and extending in a second direction across the first direction, a first gate contact formed on the second gate line arranged between the first gate line and the third gate line, and electrically connecting the cut second gate line, a second gate contact formed on the first gate line, a third gate contact formed on the third gate line, a first metal line electrically connecting the second gate contact and the third gate contact, and a second metal line electrically connected to the first gate contact.