公开(公告)号：US20240258230A1

公开(公告)日：2024-08-01

申请号：US18515463

申请日：2023-11-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungkeun Lim ,  Dohyun Go ,  Unki Kim ,  Hyohoon Byeon ,  Yuyeong Jo ,  Jinyeong Joe

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/29 ,  H01L23/31

CPC classification number: H01L23/5226 ,  H01L21/76898 ,  H01L23/291 ,  H01L23/3171

Abstract: A semiconductor device includes a substrate; an active region extending on the substrate in a first direction; a protective layer on a lower surface of the substrate; an etch stop layer on a lower surface of the protective layer; a device isolation layer defining the active region; a gate structure on the active region and extending in a second direction, intersecting the first direction; a source/drain region on the active region on both lateral sides of the gate structure; a contact structure connected to the source/drain region; and a power transmission structure electrically connected to the contact structure.

公开(公告)号：US20230387234A1

公开(公告)日：2023-11-30

申请号：US18189538

申请日：2023-03-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyohoon Byeon ,  Sungkeun Lim ,  Dohyun Go ,  Unki Kim ,  Yuyeong Jo ,  Jinyeong Joe

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L29/775 ,  H01L29/06

CPC classification number: H01L29/42392 ,  H01L29/66545 ,  H01L29/78696 ,  H01L29/775 ,  H01L29/0673 ,  H01L29/66553

Abstract: A semiconductor device includes a substrate including an active region extending in a first direction, a gate structure intersecting the active region on the substrate and extending in a second direction, a plurality of channel layers spaced apart from each other in a third direction, perpendicular to an upper surface of the substrate, on the active region and surrounded by the gate structure, and source/drain regions in recess regions of the active region, on opposite sides adjacent to the gate structure and electrically connected to the plurality of channel layers. Each of the plurality of channel layers includes first to third semiconductor layers sequentially stacked in the third direction, the first and third semiconductor layers include silicon (Si), and the second semiconductor layer includes silicon-germanium (SiGe). Side surfaces of the first to third semiconductor layers in the second direction are in contact with the gate structure.

公开(公告)号：US20230141852A1

公开(公告)日：2023-05-11

申请号：US17866966

申请日：2022-07-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanggil Lee ,  Jungtaek Kim ,  Dohyun Go ,  Pankwi Park ,  Dongsuk Shin ,  Namkyu Cho ,  Ryong Ha ,  Yang Xu

IPC: H01L29/78 ,  H01L29/08 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/7848 ,  H01L29/0847 ,  H01L21/823814 ,  H01L27/0922

Abstract: A semiconductor device includes a semiconductor active region having a vertical stack of multiple spaced-apart semiconductor channel regions thereon. A gate electrode extends on the active region and between the spaced-apart channel regions. A source/drain region contacts the spaced-apart channel regions. The source/drain region includes a stack of at least first, second and third epitaxial layers having different electrical characteristics. The first epitaxial layer contacts the active region and each of the spaced-apart channel regions. The second epitaxial layer contacts a first portion of an upper surface of the first epitaxial layer. The third epitaxial layer contacts a second portion of the upper surface of the first epitaxial layer. Each of the first, second and third epitaxial layers includes silicon germanium (SiGe) with unequal levels of germanium (Ge) therein. A level of germanium in the third epitaxial layer exceeds a level of germanium in the second epitaxial layer, which exceeds a level of germanium in the first epitaxial layer.