公开(公告)号：US20250107185A1

公开(公告)日：2025-03-27

申请号：US18738197

申请日：2024-06-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyohoon BYEON ,  Seokhoon Kim ,  Pankwi Park ,  Sungkeun Lim ,  Yuyeong Jo

IPC: H01L29/08 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device includes a substrate including an active pattern, a channel pattern on the active pattern, and including a plurality of semiconductor patterns spaced apart from each other and vertically stacked, a gate electrode on the plurality of semiconductor patterns, and extending in a first horizontal direction, a gate spacer disposed on a sidewall of the gate electrode in a second horizontal direction crossing the first horizontal direction, a source/drain pattern electrically connected to the plurality of semiconductor patterns, and including a first epitaxial pattern and a second epitaxial pattern on a side surface of the first epitaxial pattern in the second horizontal direction, and a protection pattern between at least one of the plurality of semiconductor patterns and the gate spacer and including a material having an etch selectivity with the first epitaxial pattern.

公开(公告)号：US11322583B2

公开(公告)日：2022-05-03

申请号：US16821565

申请日：2020-03-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungkeun Lim ,  Unki Kim ,  Yuyeong Jo ,  Yihwan Kim ,  Jinbum Kim ,  Pankwi Park ,  Ilgyou Shin ,  Seunghun Lee

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02

Abstract: A semiconductor device includes; an active region; an isolation region defining the active region; a barrier layer on the active region; an upper semiconductor layer on the barrier layer; and a gate structure covering an upper surface, a lower surface, and side surfaces of the upper semiconductor layer in a first direction. The first direction is a direction parallel to an upper surface of the active region, and the barrier layer is disposed between the gate structure and the active region.

公开(公告)号：US20200373385A1

公开(公告)日：2020-11-26

申请号：US16821565

申请日：2020-03-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungkeun Lim ,  Unki Kim ,  Yuyeong Jo ,  Yihwan Kim ,  Jinbum Kim ,  Pankwi Park ,  Ilgyou Shin ,  Seunghun Lee

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78

Abstract: A semiconductor device includes; an active region; an isolation region defining the active region; a barrier layer on the active region; an upper semiconductor layer on the barrier layer; and a gate structure covering an upper surface, a lower surface, and side surfaces of the upper semiconductor layer in a first direction. The first direction is a direction parallel to an upper surface of the active region, and the barrier layer is disposed between the gate structure and the active region.

公开(公告)号：US20250169152A1

公开(公告)日：2025-05-22

申请号：US18796604

申请日：2024-08-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungkeun Lim ,  Dongwoo Kim ,  Hyojin Kim ,  Pankwi Park ,  Youngdae Cho

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/161 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: An integrated circuit device includes a substrate provided with a fin-type active region which is disposed at a first surface of the substrate, a plurality of nanosheets disposed on a top surface of the fin-type active region and separated from the top surface of the fin-type active region, a gate line disposed on the fin-type active region, the gate line surrounding each of the plurality of nanosheets, a source/drain region disposed on the fin-type active region, a sidewall of the source/drain region being adjacent to the gate line and in contact with the plurality of nanosheets, a backside contact extending from a second surface of the substrate toward a lower portion of the source/drain region, and a high-concentration doped layer disposed in the lower portion of the source/drain region. The high-concentration doped layer has a dopant concentration greater than a dopant concentration of the source/drain region.

公开(公告)号：US20240297215A1

公开(公告)日：2024-09-05

申请号：US18658794

申请日：2024-05-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungkeun Lim ,  Unki Kim ,  Yuyeong Jo ,  Yihwan Kim ,  Jinbum Kim ,  Pankwi Park ,  Ilgyou Shin ,  Seunghun Lee

IPC: H01L29/06 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0638 ,  H01L21/0245 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes; an active region; an isolation region defining the active region; a barrier layer on the active region; an upper semiconductor layer on the barrier layer; and a gate structure covering an upper surface, a lower surface, and side surfaces of the upper semiconductor layer in a first direction. The first direction is a direction parallel to an upper surface of the active region, and the barrier layer is disposed between the gate structure and the active region.

公开(公告)号：US20240258230A1

公开(公告)日：2024-08-01

申请号：US18515463

申请日：2023-11-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungkeun Lim ,  Dohyun Go ,  Unki Kim ,  Hyohoon Byeon ,  Yuyeong Jo ,  Jinyeong Joe

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/29 ,  H01L23/31

CPC classification number: H01L23/5226 ,  H01L21/76898 ,  H01L23/291 ,  H01L23/3171

Abstract: A semiconductor device includes a substrate; an active region extending on the substrate in a first direction; a protective layer on a lower surface of the substrate; an etch stop layer on a lower surface of the protective layer; a device isolation layer defining the active region; a gate structure on the active region and extending in a second direction, intersecting the first direction; a source/drain region on the active region on both lateral sides of the gate structure; a contact structure connected to the source/drain region; and a power transmission structure electrically connected to the contact structure.

公开(公告)号：US20230402458A1

公开(公告)日：2023-12-14

申请号：US18196191

申请日：2023-05-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinyeong Joe ,  Hyohoon Byeon ,  Namhyun Lee ,  Sungkeun Lim ,  Yuyeong Jo

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/417 ,  H01L29/775 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L27/0922 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/42392 ,  H01L29/41733 ,  H01L29/775 ,  H01L21/8221 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66439 ,  H01L29/66545

Abstract: A semiconductor device includes a first transistor structure on a substrate, the first transistor structure including first channel layers spaced apart from each other, a first gate electrode surrounding the first channel layers, a first source/drain region connected to the first channel layers on a first side of the first gate electrode, and a second source/drain region connected to the first channel layers on a second side of the first gate electrode that is opposite to the first side of the first gate electrode, and a second transistor structure on the first transistor structure, the second transistor structure including second channel layers spaced apart from each other, a second gate electrode surrounding the second channel layers, and a third source/drain region connected to the second channel layers on a first side of the second gate electrode.

公开(公告)号：US20230387234A1

公开(公告)日：2023-11-30

申请号：US18189538

申请日：2023-03-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyohoon Byeon ,  Sungkeun Lim ,  Dohyun Go ,  Unki Kim ,  Yuyeong Jo ,  Jinyeong Joe

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L29/775 ,  H01L29/06

CPC classification number: H01L29/42392 ,  H01L29/66545 ,  H01L29/78696 ,  H01L29/775 ,  H01L29/0673 ,  H01L29/66553

Abstract: A semiconductor device includes a substrate including an active region extending in a first direction, a gate structure intersecting the active region on the substrate and extending in a second direction, a plurality of channel layers spaced apart from each other in a third direction, perpendicular to an upper surface of the substrate, on the active region and surrounded by the gate structure, and source/drain regions in recess regions of the active region, on opposite sides adjacent to the gate structure and electrically connected to the plurality of channel layers. Each of the plurality of channel layers includes first to third semiconductor layers sequentially stacked in the third direction, the first and third semiconductor layers include silicon (Si), and the second semiconductor layer includes silicon-germanium (SiGe). Side surfaces of the first to third semiconductor layers in the second direction are in contact with the gate structure.

公开(公告)号：US11728347B2

公开(公告)日：2023-08-15

申请号：US17494275

申请日：2021-10-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Weonhong Kim ,  Pilkyu Kang ,  Yuichiro Sasaki ,  Sungkeun Lim ,  Yongho Ha ,  Sangjin Hyun ,  Kughwan Kim ,  Seungha Oh

IPC: H01L27/12 ,  H01L21/762 ,  H01L27/02 ,  H01L29/78

CPC classification number: H01L27/1203 ,  H01L21/76224 ,  H01L27/0203 ,  H01L27/02 ,  H01L29/78

Abstract: An integrated circuit device includes an embedded insulation layer, a semiconductor layer on the embedded insulation layer, the semiconductor layer having a main surface, and a plurality of fin-type active areas protruding from the main surface to extend in a first horizontal direction and in parallel with one another, a separation insulation layer separating the semiconductor layer into at least two element regions adjacent to each other in a second horizontal direction intersecting the first horizontal direction, source/drain regions on the plurality of fin-type active areas, a first conductive plug on and electrically connected to the source/drain regions, a buried rail electrically connected to the first conductive plug while penetrating through the separation insulation layer and the semiconductor layer, and a power delivery structure arranged in the embedded insulation layer, the power delivery structure being in contact with and electrically connected to the buried rail.

公开(公告)号：US12224357B2

公开(公告)日：2025-02-11

申请号：US17804102

申请日：2022-05-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinyeong Joe ,  Dongchan Suh ,  Sungkeun Lim ,  Seokhoon Kim ,  Pankwi Park ,  Dongsuk Shin

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a first active region, a second active region spaced apart from the first active region, a plurality of first channel layers disposed on the first active region, and a second channel layer disposed on the second active region. The semiconductor device further includes a first gate structure intersecting the first active region and the first channel layers, a second gate structure intersecting the second active region and the second channel layer, a first source/drain region disposed on the first active region and contacting the plurality of first channel layers, and a second source/drain region and contacting the second channel layer. The plurality of first channel layers includes a first uppermost channel layer and first lower channel layers disposed below the first uppermost channel layer, and the first uppermost channel layer includes a material that is different from a material included in the first lower channel layers.