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公开(公告)号：US20230402510A1
公开(公告)日：2023-12-14
申请号：US18100872
申请日：2023-01-24
发明人： Namkyu CHO , Jungtaek Kim , Moon Seung Yang , Sumin Yu , Seojin Jeong , Seokhoon Kim , Pankwi Park
IPC分类号： H01L29/08 , H01L29/06 , H01L29/423 , H01L29/775 , H01L29/66
CPC分类号： H01L29/0847 , H01L29/0673 , H01L29/42392 , H01L29/775 , H01L29/66439
摘要： A semiconductor device includes a substrate including an active pattern, a channel pattern on the active pattern, and a source/drain pattern on a side surface of the channel pattern, the source/drain pattern including a first section between a first level and a second level that is higher than the first level, a first variation section between the second level and a third level that is higher than the second level, and a second section between the third level and a fourth level that is higher than the third level, where a rate of change in germanium concentration in the first variation section in a first direction is greater than a rate of change in germanium concentration in each of the first section and the second section in the first direction, and a germanium concentration at each of the first level and the second level is greater than 0 at % and equal to or less than 10 at %.
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公开(公告)号：US20230395662A1
公开(公告)日：2023-12-07
申请号：US18299086
申请日：2023-04-12
发明人： Seojin Jeong , Jungtaek Kim , Moonseung Yang , Sumin Yu , Namkyu Cho , Seokhoon Kim , Pankwi Park
IPC分类号： H01L29/08 , H01L29/775 , H01L29/423 , H01L29/06
CPC分类号： H01L29/0847 , H01L29/775 , H01L29/42392 , H01L29/0673
摘要： Semiconductor device may include an active region extending in a first direction, channel layers spaced apart from each other in a vertical direction, a gate structure extending on the active region and the channel layers to surround the channel layers and extending in a second direction, and a source/drain region on the active region adjacent to a side of the gate structure and contacting the plurality of channel layers. The source/drain region includes first to sixth epitaxial layers that are sequentially stacked in the vertical direction and have respective first to sixth germanium (Ge) concentrations. The first Ge concentration is lower than the second Ge concentration, the third Ge concentration is lower than the second Ge concentration and the fourth Ge concentration, and the fifth Ge concentration is lower than the fourth Ge concentration and the sixth Ge concentration.
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公开(公告)号：US11195954B2
公开(公告)日：2021-12-07
申请号：US16732864
申请日：2020-01-02
发明人： Youngdae Cho , Sunguk Jang , Sujin Jung , Jungtaek Kim , Sihyung Lee
IPC分类号： H01L29/78 , H01L29/423
摘要： A semiconductor device may include semiconductor patterns, a gate structure, a first spacer, a first semiconductor layer and a second semiconductor layer. The semiconductor patterns may be formed on a substrate, and may be spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate and may overlap in the vertical direction. The gate structure may be formed on the substrate and the semiconductor patterns. At least portion of the gate structure may be formed vertically between the semiconductor patterns. The first spacer may cover opposite sidewalls of the gate structure, the sidewalls opposite to each other in a first direction. The first semiconductor layer may cover the sidewalls of the semiconductor patterns in the first direction, and surfaces of the first spacer and the substrate. The first semiconductor layer may have a first concentration of impurities. The second semiconductor layer may be formed on the first semiconductor layer, and may have a second concentration of impurities different from the first concentration of impurities. The semiconductor device may have good characteristics and high reliability.
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公开(公告)号：US11710772B2
公开(公告)日：2023-07-25
申请号：US17560865
申请日：2021-12-23
发明人： Eunhye Choi , Seung Mo Kang , Jungtaek Kim , Moon Seung Yang , Jongryeol Yoo
IPC分类号： H01L29/10 , H01L29/08 , H01L29/78 , H01L29/423 , H01L29/66
CPC分类号： H01L29/105 , H01L29/0852 , H01L29/1079 , H01L29/42356 , H01L29/66712 , H01L29/7802
摘要： A semiconductor device including an insulating layer on a substrate; channel semiconductor patterns stacked on the insulating layer and vertically spaced apart from each other; a gate electrode crossing the channel semiconductor patterns; source/drain regions respectively at both sides of the gate electrode and connected to each other through the channel semiconductor patterns, the source/drain regions having concave bottom surfaces; and air gaps between the insulating layer and the bottom surfaces of the source/drain regions.
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5.发明公开公开(公告)号：US20230141852A1
公开(公告)日：2023-05-11
申请号：US17866966
申请日：2022-07-18
发明人： Sanggil Lee , Jungtaek Kim , Dohyun Go , Pankwi Park , Dongsuk Shin , Namkyu Cho , Ryong Ha , Yang Xu
IPC分类号： H01L29/78 , H01L29/08 , H01L21/8238 , H01L27/092
CPC分类号： H01L29/7848 , H01L29/0847 , H01L21/823814 , H01L27/0922
摘要： A semiconductor device includes a semiconductor active region having a vertical stack of multiple spaced-apart semiconductor channel regions thereon. A gate electrode extends on the active region and between the spaced-apart channel regions. A source/drain region contacts the spaced-apart channel regions. The source/drain region includes a stack of at least first, second and third epitaxial layers having different electrical characteristics. The first epitaxial layer contacts the active region and each of the spaced-apart channel regions. The second epitaxial layer contacts a first portion of an upper surface of the first epitaxial layer. The third epitaxial layer contacts a second portion of the upper surface of the first epitaxial layer. Each of the first, second and third epitaxial layers includes silicon germanium (SiGe) with unequal levels of germanium (Ge) therein. A level of germanium in the third epitaxial layer exceeds a level of germanium in the second epitaxial layer, which exceeds a level of germanium in the first epitaxial layer.
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公开(公告)号：US20200381546A1
公开(公告)日：2020-12-03
申请号：US16732864
申请日：2020-01-02
发明人： Youngdae Cho , Sunguk Jang , Sujin Jung , Jungtaek Kim , Sihyung Lee
IPC分类号： H01L29/78 , H01L29/423
摘要： A semiconductor device may include semiconductor patterns, a gate structure, a first spacer, a first semiconductor layer and a second semiconductor layer. The semiconductor patterns may be formed on a substrate, and may be spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate and may overlap in the vertical direction. The gate structure may be formed on the substrate and the semiconductor patterns. At least portion of the gate structure may be formed vertically between the semiconductor patterns. The first spacer may cover opposite sidewalls of the gate structure, the sidewalls opposite to each other in a first direction. The first semiconductor layer may cover the sidewalls of the semiconductor patterns in the first direction, and surfaces of the first spacer and the substrate. The first semiconductor layer may have a first concentration of impurities. The second semiconductor layer may be formed on the first semiconductor layer, and may have a second concentration of impurities different from the first concentration of impurities. The semiconductor device may have good characteristics and high reliability.
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公开(公告)号：US20240105776A1
公开(公告)日：2024-03-28
申请号：US18229349
申请日：2023-08-02
发明人： Namkyu Cho , Seokhoon Kim , Jungtaek Kim , Pankwi Park , Seojin Jeong
IPC分类号： H01L29/08 , H01L21/02 , H01L29/06 , H01L29/161 , H01L29/423 , H01L29/66 , H01L29/775
CPC分类号： H01L29/0847 , H01L21/02532 , H01L21/02658 , H01L29/0673 , H01L29/161 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/775
摘要： A semiconductor device includes a substrate including an active region extending in a first direction, a gate structure intersecting the active region on the substrate and extending in a second direction, where the active region includes a recessed region at at least one side of the gate structure, a plurality of channel layers on the active region, spaced apart from each other in a third direction that is substantially perpendicular to an upper surface of the substrate, and at least partially surrounded by the gate structure and a source/drain region in the recessed region of the active region and connected to the plurality of channel layers.
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公开(公告)号：US11777032B2
公开(公告)日：2023-10-03
申请号：US17533499
申请日：2021-11-23
发明人： Youngdae Cho , Sunguk Jang , Sujin Jung , Jungtaek Kim , Sihyung Lee
IPC分类号： H01L29/78 , H01L29/423
CPC分类号： H01L29/785 , H01L29/42356 , H01L29/42392 , H01L2029/7858
摘要： A semiconductor device may include semiconductor patterns, a gate structure, a first spacer, a first semiconductor layer and a second semiconductor layer. The semiconductor patterns may be formed on a substrate, and may be spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate and may overlap in the vertical direction. The gate structure may be formed on the substrate and the semiconductor patterns. At least portion of the gate structure may be formed vertically between the semiconductor patterns. The first spacer may cover opposite sidewalls of the gate structure, the sidewalls opposite to each other in a first direction. The first semiconductor layer may cover the sidewalls of the semiconductor patterns in the first direction, and surfaces of the first spacer and the substrate. The first semiconductor layer may have a first concentration of impurities. The second semiconductor layer may be formed on the first semiconductor layer, and may have a second concentration of impurities different from the first concentration of impurities. The semiconductor device may have good characteristics and high reliability.
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公开(公告)号：US20220190109A1
公开(公告)日：2022-06-16
申请号：US17467944
申请日：2021-09-07
发明人： Minhee Choi , Seojin Jeong , Seokhoon Kim , Jungtaek Kim , Pankwi Park , Moonseung Yang , Ryong Ha
IPC分类号： H01L29/06 , H01L29/786 , H01L29/66
摘要： An integrated circuit device includes a fin-type active region on a substrate; at least one nanosheet having a bottom surface facing the fin top; a gate line on the fin-type active region; and a source/drain region on the fin-type active region, adjacent to the gate line, and in contact with the at least one nanosheet, wherein the source/drain region includes a lower main body layer and an upper main body layer, a top surface of the lower main body layer includes a lower facet declining toward the substrate as it extends in a direction from the at least one nanosheet to a center of the source/drain region, and the upper main body layer includes a bottom surface contacting the lower facet and a top surface having an upper facet. With respect to a vertical cross section, the lower facet extends along a corresponding first line and the upper facet extends along a second line that intersects the first line.
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公开(公告)号：US11264381B2
公开(公告)日：2022-03-01
申请号：US16841806
申请日：2020-04-07
发明人： Seungryul Lee , Yongseung Kim , Jungtaek Kim , Pankwi Park , Dongchan Suh , Moonseung Yang , Seojin Jeong , Minhee Choi , Ryong Ha
IPC分类号： H01L27/088 , H01L21/8234 , H01L29/423 , H01L29/78 , H01L29/06
摘要： An integrated circuit device includes a fin-type active region protruding from a substrate and extending in a first direction, a plurality of semiconductor patterns disposed apart from an upper surface of the fin-type active region, the plurality of semiconductor patterns each including a channel region; a gate electrode surrounding the plurality of semiconductor patterns, extending in a second direction perpendicular to the first direction, and including a main gate electrode, which is disposed on an uppermost semiconductor pattern of the plurality of semiconductor patterns and extends in the second direction, and a sub-gate electrode disposed between the plurality of semiconductor patterns; a spacer structure disposed on both sidewalls of the main gate electrode; and a source/drain region connected to the plurality of semiconductor patterns, disposed at both sides of the gate electrode, and contacting a bottom surface of the spacer structure.
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