Abstract:
Provided is a memory device including a delay circuit having gate insulation films with thicknesses different from each other. The memory device includes a delay circuit configured to input an input signal and output an output signal, and circuit blocks configured to control an operation of reading or writing memory cell data in response to the input signal or the output signal. One of transistors constituting a circuit block has a gate insulation film having such a thickness that an effect of negative biased temperature instability (NBTI) or positive biased temperature instability (PBTI) on the transistors is minimized. The delay circuit may be affected little by a shift in a threshold voltage that may be caused by NTBI or PBTI, and thus, achieve target delay time.
Abstract:
Provided is a memory device including a delay circuit having gate insulation films with thicknesses different from each other. The memory device includes a delay circuit configured to input an input signal and output an output signal, and circuit blocks configured to control an operation of reading or writing memory cell data in response to the input signal or the output signal. One of transistors constituting a circuit block has a gate insulation film having such a thickness that an effect of negative biased temperature instability (NBTI) or positive biased temperature instability (PBTI) on the transistors is minimized. The delay circuit may be affected little by a shift in a threshold voltage that may be caused by NTBI or PBTI, and thus, achieve target delay time.
Abstract:
Provided herein is a display apparatus, a method thereof, a server, a method thereof, and a system including the display apparatus and the server. The display apparatus includes: a display configured to display a screen; and a processor configured to output for display, on the screen, a virtual channel list that includes at least one channel to which web-based service information is mapped, and to output for display, on the screen, a web content obtainable through a web-based service of the at least one channel of the virtual channel list according to a predetermined event.
Abstract:
A semiconductor memory device includes a power decoupling capacitor (PDC) for preventing effective capacitance reduction during a high frequency operation. The semiconductor memory device includes the PDC to which a cell capacitor type decoupling capacitor is connected in series. The PDC includes a metal conductive layer electrically connected in parallel to a conductive layer formed on the same level as a bit line of a cell array region, wherein a plurality of decoupling capacitors in a first group and a plurality of decoupling capacitors in a second group are respectively connected to each other in parallel in a peripheral circuit region, and a storage electrode of the first group and a storage electrode of the second group are electrically connected to each other in series through the conductive layer.
Abstract:
A semiconductor memory device includes a power decoupling capacitor (PDC) for preventing effective capacitance reduction during a high frequency operation. The semiconductor memory device includes the PDC to which a cell capacitor type decoupling capacitor is connected in series. The PDC includes a metal conductive layer electrically connected in parallel to a conductive layer formed on the same level as a bit line of a cell array region, wherein a plurality of decoupling capacitors in a first group and a plurality of decoupling capacitors in a second group are respectively connected to each other in parallel in a peripheral circuit region, and a storage electrode of the first group and a storage electrode of the second group are electrically connected to each other in series through the conductive layer.