公开(公告)号：US20230420355A1

公开(公告)日：2023-12-28

申请号：US18130197

申请日：2023-04-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunkyul Oh ,  Chonghee LEE ,  Keunho JANG ,  Yunrae CHO

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L23/3128 ,  H01L24/13 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H10B80/00

Abstract: A semiconductor package includes a package substrate including a redistribution layer including first pads and second pads on an upper surface thereof and a solder mask layer having an opening exposing the first pads entirely and exposing at least portion of each of the second pads, a semiconductor chip on the upper surface of the package substrate and including connection pads electrically connected to the redistribution layer, connection bumps below the semiconductor chip and connecting the connection pads to the first pads, and a non-conductive film layer between the semiconductor chip and the package substrate, wherein the second pads are respectively disposed on both sides of the first pads at least in a first direction, and the connection bumps are spaced apart from the second pads and the solder mask layer in the first direction.

公开(公告)号：US12119329B2

公开(公告)日：2024-10-15

申请号：US18448284

申请日：2023-08-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunkyul Oh ,  Yunrae Cho ,  Taeheon Kim ,  Seunghun Han

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/66 ,  H01L21/768 ,  H01L21/78 ,  H01L23/48 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L21/565 ,  H01L21/76898 ,  H01L21/78 ,  H01L22/12 ,  H01L22/32 ,  H01L23/481 ,  H01L24/14 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/14517 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2225/06596

Abstract: The present disclosure relates to a semiconductor package and a manufacturing method thereof. The method includes stacking semiconductor chips using a thermo-compression bonding (TCB) method, where defects are minimized for increased reliability. The semiconductor package includes an interface chip including a first test pad, a bump pad provided inside the first test pad, and a first through silicon via (TSV) provided between the first test pad and the bump pad; at least one memory chip, which is stacked on the interface chip and includes a second test pad, a dummy pad provided inside the second test pad, and a second TSV provided between the second test pad and the dummy pad; and an adhesive layer provided between the interface chip and the at least one memory chip. wherein no bump is provided on the first test pad and the second test pad.

公开(公告)号：US11257794B2

公开(公告)日：2022-02-22

申请号：US17030588

申请日：2020-09-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonjun Song ,  Eunkyul Oh ,  Hyeongmun Kang ,  Jungmin Ko

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/31 ,  H01L23/367 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

Abstract: A semiconductor package may include a package substrate, semiconductor chips, signal bumps, and first and second heat dissipation bumps. The semiconductor chips may be stacked on an upper surface of the package substrate, have first and second regions having different heat dissipation efficiencies. The second temperature may be higher than the first temperature. The signal bumps may be arranged between the semiconductor chips. The first heat dissipation bumps may be arranged between the semiconductor chips in the first region by a first pitch. The second heat dissipation bumps may be arranged between the semiconductor chips in the second region by a second pitch narrower than the first pitch. Heat generated from the second region of the semiconductor chips may be dissipated through the second heat dissipation bumps, which may be relatively closely arranged with each other.

公开(公告)号：US11769755B2

公开(公告)日：2023-09-26

申请号：US17662162

申请日：2022-05-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunkyul Oh ,  Yunrae Cho ,  Taeheon Kim ,  Seunghun Han

IPC: H01L21/56 ,  H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L21/66 ,  H01L21/768 ,  H01L21/78 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L21/565 ,  H01L21/76898 ,  H01L21/78 ,  H01L22/12 ,  H01L22/32 ,  H01L23/481 ,  H01L24/14 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/14517 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2225/06596

Abstract: The present disclosure relates to a semiconductor package and a manufacturing method thereof. The method includes stacking semiconductor chips using a thermo-compression bonding (TCB) method, where defects are minimized for increased reliability. The semiconductor package includes an interface chip including a first test pad, a bump pad provided inside the first test pad, and a first through silicon via (TSV) provided between the first test pad and the bump pad; at least one memory chip, which is stacked on the interface chip and includes a second test pad, a dummy pad provided inside the second test pad, and a second TSV provided between the second test pad and the dummy pad; and an adhesive layer provided between the interface chip and the at least one memory chip. wherein no bump is provided on the first test pad and the second test pad.

公开(公告)号：US11658160B2

公开(公告)日：2023-05-23

申请号：US17574953

申请日：2022-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonjun Song ,  Eunkyul Oh ,  Hyeongmun Kang ,  Jungmin Ko

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/31 ,  H01L23/367 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/4871 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/367 ,  H01L24/14 ,  H01L25/50 ,  H01L2224/1403 ,  H01L2224/14132 ,  H01L2224/14519 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2225/06589

Abstract: A semiconductor package may include a package substrate, semiconductor chips, signal bumps, and first and second heat dissipation bumps. The semiconductor chips may be stacked on an upper surface of the package substrate, have first and second regions having different heat dissipation efficiencies. The second temperature may be higher than the first temperature. The signal bumps may be arranged between the semiconductor chips. The first heat dissipation bumps may be arranged between the semiconductor chips in the first region by a first pitch. The second heat dissipation bumps may be arranged between the semiconductor chips in the second region by a second pitch narrower than the first pitch. Heat generated from the second region of the semiconductor chips may be dissipated through the second heat dissipation bumps, which may be relatively closely arranged with each other.

公开(公告)号：US11335668B2

公开(公告)日：2022-05-17

申请号：US16896897

申请日：2020-06-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunkyul Oh ,  Yunrae Cho ,  Taeheon Kim ,  Seunghun Han

IPC: H01L23/48 ,  H01L21/78 ,  H01L25/065 ,  H01L23/00 ,  H01L21/66 ,  H01L21/56 ,  H01L21/768 ,  H01L25/00 ,  H01L25/18

Abstract: The present disclosure relates to a semiconductor package and a manufacturing method thereof. The method includes stacking semiconductor chips using a thermo-compression bonding (TCB) method, where defects are minimized for increased reliability. The semiconductor package includes an interface chip including a first test pad, a bump pad provided inside the first test pad, and a first through silicon via (TSV) provided between the first test pad and the bump pad; at least one memory chip, which is stacked on the interface chip and includes a second test pad, a dummy pad provided inside the second test pad, and a second TSV provided between the second test pad and the dummy pad; and an adhesive layer provided between the interface chip and the at least one memory chip. wherein no bump is provided on the first test pad and the second test pad.