公开(公告)号：US20150255123A1

公开(公告)日：2015-09-10

申请号：US14571634

申请日：2014-12-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： STEVE SUNHOM PAAK ,  KANGWOOK PARK ,  HEONJONG SHIN ,  SUNIL YU ,  JONGMIL YOUN ,  HYUNGSOON JANG

IPC: G11C5/06 ,  G11C5/02

CPC classification number: G11C5/06 ,  G11C5/02 ,  G11C5/025 ,  G11C8/14 ,  G11C29/1201 ,  G11C29/48 ,  G11C2029/5602

Abstract: A semiconductor device may include a semiconductor substrate; a test circuit array region; a pad region on the semiconductor substrate and at at least a first side of the test circuit array region and outside of the test circuit array region, transistors arranged in the test circuit array region in a first direction and a second direction perpendicular to the first direction, source lines spaced apart from each other in the second direction, each of the source lines extending in the first direction and electrically connected to corresponding source electrodes of the transistors, and drain lines spaced apart from each other in the second direction, each of the drain lines extending in the first direction and electrically connected to drain electrodes of the transistors.

Abstract translation: 半导体器件可以包括半导体衬底; 测试电路阵列区域; 半导体衬底上的焊盘区域和测试电路阵列区域的至少第一侧以及测试电路阵列区域的外部，在第一方向和垂直于第一方向的第二方向上布置在测试电路阵列区域中的晶体管 在第二方向上彼此间隔开的源极线，每个源极线在第一方向上延伸并且电连接到晶体管的相应源电极，以及在第二方向彼此间隔开的漏极线， 漏极线在第一方向上延伸并电连接到晶体管的漏电极。

公开(公告)号：US20220020860A1

公开(公告)日：2022-01-20

申请号：US17488443

申请日：2021-09-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DOOHYUN LEE ,  HEONJONG SHIN ,  MINCHAN GWAK ,  HYUNHO PARK ,  SUNGHUN JUNG ,  YONGSIK JEONG ,  SANGWON JEE ,  INCHAN HWANG

IPC: H01L29/45 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L21/8238 ,  H01L27/092

Abstract: A semiconductor device including: a substrate that includes a first active region and a second active region; a first source/drain pattern on the first active region; a second source/drain pattern on the second active region; a separation dielectric pattern on the substrate between the first source/drain pattern and the second source/drain pattern; and a first contact pattern on the first source/drain pattern, wherein the first contact pattern includes: a first metal pattern; a first barrier pattern between the first metal pattern and the first source/drain pattern; and a second barrier pattern between the first barrier pattern and the first source/drain pattern, wherein the first barrier pattern contacts the separation dielectric pattern and extends along a sidewall of the first metal pattern adjacent to the separation dielectric pattern.

公开(公告)号：US20220238518A1

公开(公告)日：2022-07-28

申请号：US17659069

申请日：2022-04-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JAE HYUN PARK ,  HEONJONG SHIN

IPC: H01L27/088 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66

Abstract: Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device includes first and second gate patterns that are spaced apart from each other in a first direction on a substrate and extend in the first direction, a separation pattern that is disposed between and being in direct contact with the first and second gate patterns and extends in a second direction intersecting the first direction, a third gate pattern that is spaced apart in the second direction from the first gate pattern and extends in the first direction, and an interlayer dielectric layer disposed between the first gate pattern and the third gate pattern. The separation pattern includes a material different from a material of the interlayer dielectric layer. A bottom surface of the separation pattern has an uneven structure.

公开(公告)号：US20210057536A1

公开(公告)日：2021-02-25

申请号：US16829372

申请日：2020-03-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DOOHYUN LEE ,  HEONJONG SHIN ,  MINCHAN GWAK ,  HYUNHO PARK ,  SUNGHUN JUNG ,  YONGSIK JEONG ,  SANGWON JEE ,  INCHAN HWANG

IPC: H01L29/45 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L21/8238 ,  H01L29/66

Abstract: A semiconductor device including: a substrate that includes a first active region and a second active region; a first source/drain pattern on the first active region; a second source/drain pattern on the second active region; a separation dielectric pattern on the substrate between the first source/drain pattern and the second source/drain pattern; and a first contact pattern on the first source/drain pattern, wherein the first contact pattern includes: a first metal pattern; a first barrier pattern between the first metal pattern and the first source/drain pattern; and a second barrier pattern between the first barrier pattern and the first source/drain pattern, wherein the first barrier pattern contacts the separation dielectric pattern and extends along a sidewall of the first metal pattern adjacent to the separation dielectric pattern.

公开(公告)号：US20220310809A1

公开(公告)日：2022-09-29

申请号：US17841873

申请日：2022-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Doohyun Lee ,  HYUN-SEUNG SONG ,  YEONGCHANG ROH ,  HEONJONG SHIN ,  SORA YOU ,  YONGSIK JEONG

IPC: H01L29/417 ,  H01L29/49 ,  H01L23/535 ,  H01L29/08 ,  H01L29/423 ,  H01L23/532

Abstract: A semiconductor device comprising a gate electrode on a substrate, a source/drain pattern on the substrate on a side of the gate electrode, and a gate contact plug on the gate electrode are disclosed. The gate contact plug may include a first gate contact segment, and a second gate contact segment that extends in a vertical direction from a top surface of the first gate contact segment. An upper width of the first gate contact segment may be greater than a lower width of the second gate contact segment.

公开(公告)号：US20210035971A1

公开(公告)日：2021-02-04

申请号：US16825030

申请日：2020-03-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JAE HYUN PARK ,  HEONJONG SHIN

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234

Abstract: Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device includes first and second gate patterns that are spaced apart from each other in a first direction on a substrate and extend in the first direction, a separation pattern that is disposed between and being in direct contact with the first and second gate patterns and extends in a second direction intersecting the first direction, a third gate pattern that is spaced apart in the second direction from the first gate pattern and extends in the first direction, and an interlayer dielectric layer disposed between the first gate pattern and the third gate pattern. The separation pattern includes a material different from a material of the interlayer dielectric layer. A bottom surface of the separation pattern has an uneven structure.