中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

11 records (took 0.019 seconds)

    METHOD OF PATTERNING ELEMENTAL METALS
    1.
    发明申请
    METHOD OF PATTERNING ELEMENTAL METALS 有权

    公开(公告)号：US20240429065A1

    公开(公告)日：2024-12-26

    申请号：US18747387

    申请日：2024-06-18

    Applicant: Samsung Electronics Co., Ltd. ,  The Regents of the University of California

    Inventor： Jane P. Chang ,  Owen Watkins ,  Harsono S. Simka ,  Ryan Sheil

    IPC: H01L21/3213 ,  H01L21/02 ,  H01L21/033

    Abstract: A method of manufacturing an interconnect in a metal layer in a back-end-of-line of a semiconductor device includes N2 plasma passivation, through an opening a hard mask, of a ruthenium layer on a substrate. The N2 plasma passivation forms a ruthenium nitride layer on the ruthenium layer. The ruthenium nitride layer includes a first portion aligned with the opening and a second portion underneath the hard mask. The method also includes H2 plasma reduction of the ruthenium nitride layer after the N2 plasma passivation. The H2 plasma reduction removes the first portion of the ruthenium nitride layer. The method also includes O2 plasma etching the ruthenium layer after the H2 plasma reduction. The method also includes repeatedly performing the N2 plasma passivation, the H2 plasma reduction, and the O2 plasma etching to remove the ruthenium layer down to the substrate.

    LOW RESISTIVITY INTERCONNECTS FOR INTEGRATED CIRCUIT AND METHODS OF MANUFACTURING THE SAME
    3.
    发明申请
    LOW RESISTIVITY INTERCONNECTS FOR INTEGRATED CIRCUIT AND METHODS OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20200235055A1

    公开(公告)日：2020-07-23

    申请号：US16410787

    申请日：2019-05-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ganesh Hegde ,  Harsono S. Simka

    IPC: H01L23/532 ,  H01L21/768

    Abstract: A method of forming an interconnect for an integrated circuit includes: identifying an interconnect barrier material, identifying a plurality of potential dopant elements, creating an ensemble of potential barrier structures including the interconnect barrier material doped at a plurality of doping positions and a plurality of doping amounts for each of the plurality of potential dopant elements, calculating a density of states for each of the barrier structures of the ensemble, selecting a dopant element and a doping amount based on the density of states, and depositing a barrier layer including an alloy, the alloy including the interconnect barrier material and the selected dopant element at the selected doping amount.

    Method and system for providing a reverse-engineering resistant hardware embedded security module
    4.
    发明授权
    Method and system for providing a reverse-engineering resistant hardware embedded security module 有权

    公开(公告)号：US10381315B2

    公开(公告)日：2019-08-13

    申请号：US15927239

    申请日：2018-03-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Harsono S. Simka ,  Ganesh Hegde ,  Joon Goo Hong ,  Rwik Sengupta ,  Mark S. Rodder

    IPC: H01L31/062 ,  H01L23/00 ,  H01L23/522 ,  H01L27/02 ,  H04L9/32 ,  H01L23/532

    Abstract: A hardware-embedded security system is described. The system includes connective components, circuit elements and an insulator. The connective components include a variable conductivity layer that is conductive for a first stoichiometry and insulating for a second stoichiometry. The variable conductivity layer is conductive for a first portion of the connective components connected to a first portion of the circuit elements. The variable conductivity layer is insulating for a second portion of the connective components connected to a second portion of the circuit elements. Thus, the first portion of the circuit elements are active and the second portion of the circuit elements are inactive. The insulator is adjacent to at least a portion of each of the connective components. The first stoichiometry may be indistinguishable from the second stoichiometry via optical imaging and electron imaging of a portion of the insulator and the variable conductivity layer.

    Low resistivity interconnects with doped barrier layer for integrated circuits
    5.
    发明授权
    Low resistivity interconnects with doped barrier layer for integrated circuits 有权

    公开(公告)号：US11043454B2

    公开(公告)日：2021-06-22

    申请号：US16410787

    申请日：2019-05-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ganesh Hegde ,  Harsono S. Simka

    IPC: H01L23/532 ,  H01L21/768

    Abstract: A method of forming an interconnect for an integrated circuit includes: identifying an interconnect barrier material, identifying a plurality of potential dopant elements, creating an ensemble of potential barrier structures including the interconnect barrier material doped at a plurality of doping positions and a plurality of doping amounts for each of the plurality of potential dopant elements, calculating a density of states for each of the barrier structures of the ensemble, selecting a dopant element and a doping amount based on the density of states, and depositing a barrier layer including an alloy, the alloy including the interconnect barrier material and the selected dopant element at the selected doping amount.

    GENERATIVE STRUCTURE-PROPERTY INVERSE COMPUTATIONAL CO-DESIGN OF MATERIALS
    6.
    发明申请
    GENERATIVE STRUCTURE-PROPERTY INVERSE COMPUTATIONAL CO-DESIGN OF MATERIALS 有权

    公开(公告)号：US20210103822A1

    公开(公告)日：2021-04-08

    申请号：US16799410

    申请日：2020-02-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ganesh Hegde ,  Harsono S. Simka

    IPC: G06N3/08 ,  G06N3/04 ,  G06N20/20 ,  G06N20/10 ,  G06F30/13 ,  G06F30/27

    Abstract: A method and a system for material design utilizing machine learning are provided, where the underlying joint distribution p(S,P) of structure (S)-property (P) relationships is explicitly learned simultaneously and is utilized to directly generate samples (S,P) in a single step utilizing generative techniques, without any additional processing steps. The subspace of structures that meet or exceed the target for property P is then identified utilizing conditional generation of the distribution (e.g., p(P)), or through randomly generating a large number of samples (S,P) and filtering (e.g., selecting) those that meet target property criteria.

    METHOD AND SYSTEM FOR PROVIDING A REVERSE-ENGINEERING RESISTANT HARDWARE EMBEDDED SECURITY MODULE
    8.
    发明申请
    METHOD AND SYSTEM FOR PROVIDING A REVERSE-ENGINEERING RESISTANT HARDWARE EMBEDDED SECURITY MODULE 审中-公开

    公开(公告)号：US20190318998A1

    公开(公告)日：2019-10-17

    申请号：US16453475

    申请日：2019-06-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Harsono S. Simka ,  Ganesh Hegde ,  Joon Goo Hong ,  Rwik Sengupta ,  Mark S. Rodder

    IPC: H01L23/00 ,  H01L23/522 ,  H01L27/02

    Abstract: A hardware-embedded security system is described. The system includes connective components, circuit elements and an insulator. The connective components include a variable conductivity layer that is conductive for a first stoichiometry and insulating for a second stoichiometry. A first portion of the circuit elements are connected to a first portion of the connective components and are active. A the second portion of the circuit elements are connected to a second portion of the connective components and are inactive. The insulator is adjacent to at least a portion of each of the connective components. The first stoichiometry is indistinguishable from the second stoichiometry via optical imaging and electron imaging of a portion of the insulator and the variable conductivity layer.

    Generative structure-property inverse computational co-design of materials
    9.
    发明授权
    Generative structure-property inverse computational co-design of materials 有权

    公开(公告)号：US11537898B2

    公开(公告)日：2022-12-27

    申请号：US16799410

    申请日：2020-02-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ganesh Hegde ,  Harsono S. Simka

    IPC: G06N3/08 ,  G06N20/20 ,  G06N20/10 ,  G06F30/13 ,  G06F30/27 ,  G06N3/04

    Abstract: A method and a system for material design utilizing machine learning are provided, where the underlying joint distribution p(S,P) of structure (S)-property (P) relationships is explicitly learned simultaneously and is utilized to directly generate samples (S,P) in a single step utilizing generative techniques, without any additional processing steps. The subspace of structures that meet or exceed the target for property P is then identified utilizing conditional generation of the distribution (e.g., p(P)), or through randomly generating a large number of samples (S,P) and filtering (e.g., selecting) those that meet target property criteria.

Patent Agency Ranking