公开(公告)号：US20170040328A1

公开(公告)日：2017-02-09

申请号：US15333491

申请日：2016-10-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hong-bae PARK ,  Ja-hum KU ,  Myeong-cheol KIM ,  Jin-wook LEE ,  Sung-kee HAN

IPC: H01L27/11 ,  H01L27/02 ,  H01L29/06 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/02 ,  H01L23/528 ,  H01L27/092

CPC classification number: H01L27/1104 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785

Abstract: A method includes providing a plurality of active regions on a substrate, and at least a first device isolation layer between two of the plurality of active regions, wherein the plurality of active regions extend in a first direction; providing a gate layer extending in a second direction, the gate layer forming a plurality of gate lines including a first gate line and a second gate line extending in a straight line with respect to each other and having a space therebetween, each of the first gate line and second gate line crossing at least one of the active regions, providing an insulation layer covering the first device isolation layer and covering the active region around each of the first and second gate lines; and providing an inter-gate insulation region in the space between the first gate line and the second gate line.

Abstract translation: 一种方法包括在衬底上提供多个有源区，以及在所述多个有源区中的两个之间的至少第一器件隔离层，其中所述多个有源区在第一方向上延伸; 提供沿第二方向延伸的栅极层，所述栅极层形成多条栅极线，所述栅极线包括相对于彼此以直线延伸的第一栅极线和第二栅极线，所述第二栅极线和第二栅极线之间具有间隔，所述第一栅极 线和第二栅极线交叉有效区域中的至少一个，提供覆盖第一器件隔离层并围绕第一和第二栅极线周围的有源区域覆盖的绝缘层; 以及在所述第一栅极线和所述第二栅极线之间的空间中提供栅极间绝缘区域。

公开(公告)号：US20200035796A1

公开(公告)日：2020-01-30

申请号：US16404857

申请日：2019-05-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang-yeon LEE ,  Jin-wook LEE ,  Min-chan GWAK ,  Kye-Hyun BAEK ,  Hong-bae PARK

IPC: H01L29/417 ,  H01L27/088 ,  H01L29/78 ,  H01L21/8234

Abstract: An integrated circuit device including a substrate; a fin-type active region protruding from the substrate; a gate line intersecting the fin-type active region and covering a top surface and side walls thereof; a gate insulating capping layer covering the gate line; source/drain regions at sides of the gate line on the fin-type active region; first conductive plugs connected to the source/drain regions; a hard mask layer covering the first conductive plugs; and a second conductive plug between the first conductive plugs, the second conductive plug connected to the gate line by passing through the gate insulating capping layer and having a top surface higher than the top surface of each first conductive plug, wherein the hard mask layer protrudes from the first conductive plugs and toward the second conductive plug so that a portion of the hard mask layer overhangs from an edge of the first conductive plugs.

公开(公告)号：US20180277547A1

公开(公告)日：2018-09-27

申请号：US15992623

申请日：2018-05-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hong-bae PARK ,  Ja-hum KU ,  Myeong-cheol KIM ,  Jin-wook LEE ,  Sung-kee HAN

IPC: H01L27/11 ,  H01L27/092 ,  H01L27/02 ,  H01L21/8238 ,  H01L23/528 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L27/1104 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/845 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785

Abstract: A method includes providing a plurality of active regions on a substrate, and at least a first device isolation layer between two of the plurality of active regions, wherein the plurality of active regions extend in a first direction; providing a gate layer extending in a second direction, the gate layer forming a plurality of gate lines including a first gate line and a second gate line extending in a straight line with respect to each other and having a space therebetween, each of the first gate line and second gate line crossing at least one of the active regions, providing an insulation layer covering the first device isolation layer and covering the active region around each of the first and second gate lines; and providing an inter-gate insulation region in the space between the first gate line and the second gate line.

公开(公告)号：US20220223702A1

公开(公告)日：2022-07-14

申请号：US17707036

申请日：2022-03-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang-yeon LEE ,  Jin-wook LEE ,  Min-chan GWAK ,  Kye-Hyun BAEK ,  Hong-bae PARK

IPC: H01L29/417 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/78

Abstract: An integrated circuit device including a substrate; a fin-type active region protruding from the substrate; a gate line intersecting the fin-type active region and covering a top surface and side walls thereof; a gate insulating capping layer covering the gate line; source/drain regions at sides of the gate line on the fin-type active region; first conductive plugs connected to the source/drain regions; a hard mask layer covering the first conductive plugs; and a second conductive plug between the first conductive plugs, the second conductive plug connected to the gate line by passing through the gate insulating capping layer and having a top surface higher than the top surface of each first conductive plug, wherein the hard mask layer protrudes from the first conductive plugs and toward the second conductive plug so that a portion of the hard mask layer overhangs from an edge of the first conductive plugs.