公开(公告)号：US20180277547A1

公开(公告)日：2018-09-27

申请号：US15992623

申请日：2018-05-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hong-bae PARK ,  Ja-hum KU ,  Myeong-cheol KIM ,  Jin-wook LEE ,  Sung-kee HAN

IPC: H01L27/11 ,  H01L27/092 ,  H01L27/02 ,  H01L21/8238 ,  H01L23/528 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L27/1104 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/845 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785

Abstract: A method includes providing a plurality of active regions on a substrate, and at least a first device isolation layer between two of the plurality of active regions, wherein the plurality of active regions extend in a first direction; providing a gate layer extending in a second direction, the gate layer forming a plurality of gate lines including a first gate line and a second gate line extending in a straight line with respect to each other and having a space therebetween, each of the first gate line and second gate line crossing at least one of the active regions, providing an insulation layer covering the first device isolation layer and covering the active region around each of the first and second gate lines; and providing an inter-gate insulation region in the space between the first gate line and the second gate line.

公开(公告)号：US20170040328A1

公开(公告)日：2017-02-09

申请号：US15333491

申请日：2016-10-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hong-bae PARK ,  Ja-hum KU ,  Myeong-cheol KIM ,  Jin-wook LEE ,  Sung-kee HAN

IPC: H01L27/11 ,  H01L27/02 ,  H01L29/06 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/02 ,  H01L23/528 ,  H01L27/092

CPC classification number: H01L27/1104 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785

Abstract: A method includes providing a plurality of active regions on a substrate, and at least a first device isolation layer between two of the plurality of active regions, wherein the plurality of active regions extend in a first direction; providing a gate layer extending in a second direction, the gate layer forming a plurality of gate lines including a first gate line and a second gate line extending in a straight line with respect to each other and having a space therebetween, each of the first gate line and second gate line crossing at least one of the active regions, providing an insulation layer covering the first device isolation layer and covering the active region around each of the first and second gate lines; and providing an inter-gate insulation region in the space between the first gate line and the second gate line.

Abstract translation: 一种方法包括在衬底上提供多个有源区，以及在所述多个有源区中的两个之间的至少第一器件隔离层，其中所述多个有源区在第一方向上延伸; 提供沿第二方向延伸的栅极层，所述栅极层形成多条栅极线，所述栅极线包括相对于彼此以直线延伸的第一栅极线和第二栅极线，所述第二栅极线和第二栅极线之间具有间隔，所述第一栅极 线和第二栅极线交叉有效区域中的至少一个，提供覆盖第一器件隔离层并围绕第一和第二栅极线周围的有源区域覆盖的绝缘层; 以及在所述第一栅极线和所述第二栅极线之间的空间中提供栅极间绝缘区域。

公开(公告)号：US20140057427A1

公开(公告)日：2014-02-27

申请号：US14070935

申请日：2013-11-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Kwon KIM ,  Young-Ju PARK ,  Dong-Hyuk YEAM ,  Yoo-jung LEE ,  Myeong-cheol KIM ,  Do-Hyoung KIM ,  Heung-Sik PARK

IPC: H01L21/28

CPC classification number: H01L21/28132 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656

Abstract: Example embodiments relate to a method for manufacturing a semiconductor device, wherein a metal gate electrode therein may be formed without a void in a lower portion of the metal gate electrode. The method may include providing a substrate, forming a dummy gate electrode on the substrate, forming a gate spacer on the substrate to be contiguous to the dummy gate electrode, forming a first recess by simultaneously removing a portion of the dummy gate electrode and a portion of the gate spacer, the first recess having an upper end wider than a lower end, forming a second recess by removing the dummy gate electrode remaining after forming the first recess, and forming a metal gate electrode by depositing a metal to fill the first and second recesses.

Abstract translation: 示例性实施例涉及用于制造半导体器件的方法，其中可以在金属栅电极的下部中形成其中的金属栅极电极，而不产生空隙。 该方法可以包括提供衬底，在衬底上形成虚拟栅电极，在衬底上形成与虚拟栅电极相邻的栅极间隔物，通过同时去除虚拟栅电极的一部分形成第一凹槽， 所述第一凹部具有比下端更宽的上端，通过去除在形成所述第一凹部之后残留的所述虚设栅电极形成第二凹槽，以及通过沉积金属以填充所述第一凹部而形成金属栅电极，以填充所述第一凹部 第二个凹槽

公开(公告)号：US20130277720A1

公开(公告)日：2013-10-24

申请号：US13780855

申请日：2013-02-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myeong-cheol KIM ,  Cheol KIM ,  Jaehun SEO ,  YooJung LEE ,  Kisoo CHANG ,  Siyoung CHOI

IPC: H01L29/78

CPC classification number: H01L29/785 ,  H01L29/7851

Abstract: Field effect transistors include a source region and a drain region on a substrate, a fin base protruding from a top surface of the substrate, a plurality of fin portions extending upward from the fin base and connecting the source region with the drain region, a gate electrode on the fin portions, and a gate dielectric between the fin portions and the gate electrode.

Abstract translation: 场效应晶体管包括基板上的源极区域和漏极区域，从基板的顶面突出的翅片基底，从翅片基底向上延伸并将源极区域与漏极区域连接的多个翅片部分， 翅片部分之间的电极以及翅片部分和栅电极之间的栅极电介质。

公开(公告)号：US20190214394A1

公开(公告)日：2019-07-11

申请号：US16351004

申请日：2019-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Keun-hee BAI ,  Myeong-cheol KIM ,  Kwan-heum LEE ,  Do-hyoung KIM ,  Jin-wook LEE ,  Seung-mo HA ,  Dong-Hoon KHANG

IPC: H01L27/11 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/08 ,  H01L27/088

CPC classification number: H01L27/1104 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L27/0886 ,  H01L27/1116 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate, a fin active region pattern on the substrate, the fin active region pattern including an upper region and a lower region, a device isolation layer pattern surrounding the fin active region pattern, a gate pattern on the upper region of the fin active region pattern, and a stressor on the lower region of the fin active region pattern, wherein a top surface of the device isolation layer pattern is lower than a top surface of the upper region and higher than a top surface of the lower region.

公开(公告)号：US20130040452A1

公开(公告)日：2013-02-14

申请号：US13652550

申请日：2012-10-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-ju Park ,  Jae-ho MIN ,  Myeong-cheol KIM ,  Dong-chan KIM ,  Jae-hwang SIM

IPC: H01L21/28 ,  H01L21/311

CPC classification number: H01L23/528 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L23/522 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11531 ,  H01L27/11548 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices and methods of forming semiconductor devices are provided in which a plurality of patterns are simultaneously formed to have different widths and the pattern densities of some regions are increased using double patterning. The semiconductor device includes a plurality of conductive lines each including a first line portion and a second line portion, where the first line portion extends on a substrate in a first direction, the second line portion extends from one end of the first line portion in a second direction, and the first direction is different from the second direction; a plurality of contact pads each of which is connected with a respective conductive line of the plurality of conductive lines via the second line portion of the corresponding conductive line; and a plurality of dummy conductive lines each including a first dummy portion extending from a respective contact pad of the plurality of contact pads, in parallel with the corresponding second line portion in the second direction.

Abstract translation: 提供形成半导体器件的半导体器件和方法，其中同时形成多个图案以具有不同的宽度，并且使用双重图案化来增加一些区域的图案密度。 半导体器件包括多个导线，每条导线包括第一线部分和第二线部分，其中第一线部分在第一方向上在衬底上延伸，第二线部分从第一线部分的一端延伸到 第二方向，第一方向与第二方向不同; 多个接触焊盘，每个接触焊盘经由相应的导线的第二线部分与多条导线的相应导线连接; 以及多个虚设导电线，每个虚设导电线包括从所述多个接触焊盘的相应的接触焊盘延伸的第一虚设部分，与所述第二方向上的对应的第二线部分平行。