公开(公告)号：US09728516B2

公开(公告)日：2017-08-08

申请号：US15164502

申请日：2016-05-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hongbin Shi ,  Kang Joon Lee

IPC: H01L23/48 ,  H01L23/00

CPC classification number: H01L24/05 ,  H01L23/3157 ,  H01L23/49838 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/02135 ,  H01L2224/02145 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05555 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/06131 ,  H01L2224/0615 ,  H01L2224/1131 ,  H01L2224/11849 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13026 ,  H01L2224/13027 ,  H01L2224/14131 ,  H01L2224/16227 ,  H01L2924/3511 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: An electric apparatus may include a plurality of electric patterns arranged on a substrate. Each of the electric patterns may include a pad for connection with a solder ball, an electrical trace laterally extending from a portion of the pad to allow an electrical signal to be transmitted from or to the pad, a first dummy trace laterally extending from other portion of the pad, and a first connection line connecting the first dummy trace to the electrical trace. The first dummy trace may be provided at a position deviated from a straight line connecting the pad to the electrical trace.

公开(公告)号：US10050020B2

公开(公告)日：2018-08-14

申请号：US15418077

申请日：2017-01-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hongbin Shi ,  Junho Lee

IPC: H01L25/065 ,  H01L23/31

Abstract: A semiconductor package includes a lower package including a lower package substrate, a lower semiconductor chip disposed on the lower package substrate, and a lower mold layer disposed on the lower package substrate, and an upper package disposed on the lower package. The upper package includes an upper package substrate and an upper semiconductor chip disposed on the upper package substrate. The semiconductor package additionally includes connection terminals disposed between the lower and upper package substrates. The connection terminals comprise outermost connection terminals and inner connection terminals. The inner connection terminals are disposed between the lower semiconductor chip and outermost connection terminals. The semiconductor package further includes a first under-fill layer disposed between the lower package substrate and the upper package substrate. At least one of the outermost connection terminals is disposed outside of the lower mold layer.