公开(公告)号：US12119315B2

公开(公告)日：2024-10-15

申请号：US17650851

申请日：2022-02-13

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Chih-Wei Chang

IPC分类号： H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L25/065

CPC分类号： H01L24/05 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/03 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L2224/03622 ,  H01L2224/05009 ,  H01L2224/05011 ,  H01L2224/05014 ,  H01L2224/05015 ,  H01L2224/05017 ,  H01L2224/05073 ,  H01L2224/0801 ,  H01L2224/08055 ,  H01L2224/08056 ,  H01L2224/08059 ,  H01L2224/0807 ,  H01L2224/08147 ,  H01L2224/08148 ,  H01L2224/80895 ,  H01L2225/06524 ,  H01L2225/06544 ,  H01L2225/06548

摘要： A chip bonding method includes the following operations. A first chip is provided, which includes a first contact pad including a first portion lower than a first surface of a first substrate and a second portion higher than the first surface of the first substrate to form the stepped first contact pad. A second chip is provided, which includes a second contact pad including a third portion lower than a third surface of a second substrate and a fourth portion higher than the third surface of the second substrate to form the stepped second contact pad. The first chip and the second chip are bonded. The first portion of the first chip contacts with the fourth portion of the second chip, and the second portion of the first chip contacts with the third portion of the second chip.

公开(公告)号：US20240321702A1

公开(公告)日：2024-09-26

申请号：US18474166

申请日：2023-09-25

申请人： Advanced Micro Devices, Inc. ,  Xilinx, Inc.

发明人： Yan Wang ,  Kevin Gillespie ,  Samuel Naffziger ,  Richard Schultz ,  Raja Swaminathan ,  Omar Zia ,  John Wuu

IPC分类号： H01L23/498 ,  H01L23/00 ,  H01L23/367 ,  H01L25/065

CPC分类号： H01L23/49822 ,  H01L23/3675 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/32 ,  H01L25/0652 ,  H01L2224/05009 ,  H01L2224/05025 ,  H01L2224/32146 ,  H01L2224/32165 ,  H01L2924/1431 ,  H01L2924/1437 ,  H01L2924/351

摘要： A method for providing backside power can include providing a first circuit die having a first metal stack. The method can also include connecting a second metal stack of a second circuit die to the first metal stack of the first circuit die, wherein a backside power delivery network is located in a passivation layer of at least one of the first circuit die or the second circuit die. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US20240063151A1

公开(公告)日：2024-02-22

申请号：US17889485

申请日：2022-08-17

申请人： NANYA TECHNOLOGY CORPORATION

发明人： YI-JEN LO

IPC分类号： H01L23/00 ,  H01L25/065

CPC分类号： H01L24/05 ,  H01L25/0657 ,  H01L24/80 ,  H01L24/08 ,  H01L2924/30101 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/08146 ,  H01L2224/05009 ,  H01L2224/05017 ,  H01L2224/05083 ,  H01L2224/05541 ,  H01L2224/05576 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2224/05556 ,  H01L2224/05554 ,  H01L2224/05015 ,  H01L2224/05555 ,  H01L2224/05014

摘要： The present application provides a semiconductor structure having a conductive pad with a protrusion, and a manufacturing method of the semiconductor structure. The semiconductor structure includes a first die including a first substrate, a first dielectric layer over the first substrate, a first conductive pad at least partially exposed through the first dielectric layer, a first bonding layer over the first dielectric layer, and a first via extending through the first bonding layer and coupled to the first conductive pad; and a second die including a second bonding layer bonded to the first bonding layer, a second substrate over the second bonding layer, and a second via extending through the second substrate and the second bonding layer, wherein a first contact surface area between the first bonding layer and the second via is substantially greater than a second contact surface area between the first via and the second via.

公开(公告)号：US11894299B2

公开(公告)日：2024-02-06

申请号：US17188787

申请日：2021-03-01

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chao-Wen Shih ,  Chen-Hua Yu ,  Han-Ping Pu ,  Hsin-Yu Pan ,  Hao-Yi Tsai ,  Sen-Kuei Hsu

IPC分类号： H01L23/52 ,  H01L23/525 ,  H01L23/552 ,  H01L23/00 ,  H01L23/522 ,  H01L23/532 ,  H01L23/29 ,  H01L23/31 ,  H01L21/56 ,  H01L23/528 ,  H01L21/768

CPC分类号： H01L23/525 ,  H01L21/56 ,  H01L23/293 ,  H01L23/3192 ,  H01L23/5225 ,  H01L23/5329 ,  H01L23/552 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/14 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76885 ,  H01L23/5286 ,  H01L24/13 ,  H01L2224/0348 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/11622 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/16104 ,  H01L2224/03462 ,  H01L2924/00014

摘要： A method includes forming a dielectric layer over a contact pad of a device, forming a first polymer layer over the dielectric layer, forming a first conductive line and a first portion of a second conductive line over the first polymer layer, patterning a photoresist to form an opening over the first portion of the second conductive feature, wherein after patterning the photoresist the first conductive line remains covered by photoresist, forming a second portion of the second conductive line in the opening, wherein the second portion of the second conductive line physically contacts the first portion of the second conductive line, and forming a second polymer layer extending completely over the first conductive line and the second portion of the second conductive line.

公开(公告)号：US11887955B2

公开(公告)日：2024-01-30

申请号：US17412551

申请日：2021-08-26

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Hui-Min Huang ,  Ming-Da Cheng ,  Chang-Jung Hsueh ,  Wei-Hung Lin ,  Kai Jun Zhan ,  Wan-Yu Chiang

IPC分类号： H01L23/522 ,  H01L23/00

CPC分类号： H01L24/13 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/02181 ,  H01L2224/03622 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/11622 ,  H01L2224/13018

摘要： A semiconductor die including mechanical-stress-resistant bump structures is provided. The semiconductor die includes dielectric material layers embedding metal interconnect structures, a connection pad-and-via structure, and a bump structure including a bump via portion and a bonding bump portion. The entirety of a bottom surface of the bump via portion is located within an area of a horizontal top surface of a pad portion of the connection pad-and-via structure.

公开(公告)号：US11881476B2

公开(公告)日：2024-01-23

申请号：US17664841

申请日：2022-05-24

申请人： Semtech Corporation

发明人： Changjun Huang ,  Jonathan Clark

IPC分类号： H01L25/00 ,  H01L23/60 ,  H01L23/495 ,  H01L27/02 ,  H01L23/00 ,  H01L21/768 ,  H01L25/065 ,  H01L23/29 ,  H01L21/56 ,  H01L23/31 ,  H01L21/304 ,  H01L21/78

CPC分类号： H01L25/50 ,  H01L21/76898 ,  H01L23/49575 ,  H01L23/60 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L21/304 ,  H01L21/561 ,  H01L21/78 ,  H01L23/295 ,  H01L23/3121 ,  H01L23/3171 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/80 ,  H01L24/85 ,  H01L27/0255 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/0558 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06181 ,  H01L2224/08146 ,  H01L2224/08148 ,  H01L2224/1132 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/17181 ,  H01L2224/2929 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4847 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/48465 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/8082 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/8182 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/1033 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10322 ,  H01L2924/10324 ,  H01L2924/10329 ,  H01L2924/10335 ,  H01L2924/1203 ,  H01L2924/13091 ,  H01L2924/141 ,  H01L2924/143 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2224/13111 ,  H01L2924/01082 ,  H01L2224/11901 ,  H01L2224/11849 ,  H01L2224/94 ,  H01L2224/11 ,  H01L2224/94 ,  H01L2224/03 ,  H01L2224/94 ,  H01L2224/81 ,  H01L2224/97 ,  H01L2224/81 ,  H01L2224/94 ,  H01L2224/80 ,  H01L2224/97 ,  H01L2224/80 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/48145 ,  H01L2924/00012 ,  H01L2224/48465 ,  H01L2224/48247 ,  H01L2924/00 ,  H01L2224/45147 ,  H01L2924/00014 ,  H01L2224/45124 ,  H01L2924/00014 ,  H01L2224/45144 ,  H01L2924/00014 ,  H01L2224/45139 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/00

摘要： A semiconductor device has a first semiconductor die including a first protection circuit. A second semiconductor die including a second protection circuit is disposed over the first semiconductor die. A portion of the first semiconductor die and second semiconductor die is removed to reduce die thickness. An interconnect structure is formed to commonly connect the first protection circuit and second protection circuit. A transient condition incident to the interconnect structure is collectively discharged through the first protection circuit and second protection circuit. Any number of semiconductor die with protection circuits can be stacked and interconnected via the interconnect structure to increase the ESD current discharge capability. The die stacking can be achieved by disposing a first semiconductor wafer over a second semiconductor wafer and then singulating the wafers. Alternatively, die-to-wafer or die-to-die assembly is used.

公开(公告)号：US20230386980A1

公开(公告)日：2023-11-30

申请号：US18324897

申请日：2023-05-26

申请人： STMICROELECTRONICS S.r.l.

发明人： Michele DERAI ,  Guendalina CATALANO

IPC分类号： H01L23/495 ,  H01L23/29 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498

CPC分类号： H01L23/49513 ,  H01L23/29 ,  H01L21/563 ,  H01L24/03 ,  H01L24/05 ,  H01L23/49827 ,  H01L2224/05009 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05124 ,  H01L2224/05147

摘要： A semiconductor die is attached on a die-attachment portion of a substrate such as a leadframe. The semiconductor die has a front surface opposite the substrate and one or more contact pads at the front surface having an outer surface finishing of a first electrically conductive material such as NiPd or Al. An encapsulation of laser direct structuring, LDS material is molded onto the semiconductor die attached on the substrate. Laser beam energy is applied to selected locations of the front surface of the encapsulation of LDS material to activate the LDS material at the selected locations and structure therein electrically conductive formations comprising one or more vias towards the contact pad. The vias comprise a second electrically conductive material that is different from the first electrically conductive material of the outer surface finishing of the contact pad. Prior to growing the second electrically conductive material a nickel layer is formed over the outer surface finishing of the contact pad, wherein the nickel layer promotes adhesion between the second electrically conductive material and the first electrically conductive material.

公开(公告)号：US20230207528A1

公开(公告)日：2023-06-29

申请号：US18117601

申请日：2023-03-06

申请人： Samsung Electronics Co., Ltd.

发明人： Aenee Jang

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/48

CPC分类号： H01L25/0657 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L23/481 ,  H01L25/0652 ,  H01L2224/05009 ,  H01L2224/06181 ,  H01L2224/08146 ,  H01L2225/06544 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204

摘要： A semiconductor package comprising a first semiconductor chip and a second semiconductor chip disposed on the first semiconductor chip, wherein the first semiconductor chip includes a first semiconductor body, an upper pad structure, and a first through-electrode penetrating the first semiconductor body and electrically connected to the upper pad structure, and the second semiconductor chip includes a second semiconductor body, a lower bonding pad, and an internal circuit structure including a circuit element, internal circuit wirings, and a connection pad pattern disposed on the same level as the lower bonding pad, the upper pad structure includes upper bonding pads and connection wirings, the upper bonding pads are disposed at positions corresponding to the lower bonding pad and the connection pad pattern, and the internal circuit structure is electrically connected to the first through-electrode through at least one of the upper bonding pads and the connection wirings.

公开(公告)号：US20230163087A1

公开(公告)日：2023-05-25

申请号：US17944430

申请日：2022-09-14

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Minki Kim ,  Seungduk Baek ,  Won IL Lee

IPC分类号： H01L23/00 ,  H01L25/065

CPC分类号： H01L24/05 ,  H01L25/0657 ,  H01L24/08 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2224/08145 ,  H01L2924/3512 ,  H01L2224/05541 ,  H01L2224/05551 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05576 ,  H01L2224/05647 ,  H01L2224/05687 ,  H01L2224/05009 ,  H01L2224/05011 ,  H01L2224/05017 ,  H01L2224/05018 ,  H01L2224/05025 ,  H01L2224/05076 ,  H01L2224/05083 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/0239 ,  H01L2224/02331 ,  H01L2224/02381 ,  H01L2924/1434 ,  H01L2924/1431

摘要： A semiconductor package includes: a semiconductor substrate; a through electrode that penetrates the semiconductor substrate; a first pad disposed on the through electrode; and a dielectric structure disposed on the semiconductor substrate, wherein a lower portion of the dielectric structure at least partially surrounds the through electrode, wherein an upper portion of the dielectric structure at least partially surrounds the first pad, wherein the dielectric structure includes: a first dielectric pattern; an etch stop pattern disposed on the first dielectric pattern; and a second dielectric pattern spaced apart from the first dielectric pattern by the etch stop pattern, wherein the first pad is in contact with the through electrode, the first dielectric pattern, the etch stop pattern, and second dielectric pattern, and wherein a top surface of the through electrode is at a level higher than a level of a top surface of the first dielectric pattern.

公开(公告)号：US20190088619A1

公开(公告)日：2019-03-21

申请号：US15905570

申请日：2018-02-26

申请人： Toshiba Memory Corporation

发明人： Yoichiro KURITA

IPC分类号： H01L23/00 ,  H01L23/538 ,  H01L21/56 ,  H01L21/02 ,  H01L25/065

CPC分类号： H01L24/97 ,  H01L21/02107 ,  H01L21/568 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/96 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81022 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/1058 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83

摘要： A method of manufacturing a semiconductor device includes forming an insulation layer on a support body, selectively forming openings through the insulation layer, forming a conductor pattern in the openings, and above selected portions of, the insulation layer, mounting a first semiconductor element on the insulation layer and electrically connecting the first semiconductor element to the conductor pattern, forming a resin over the first semiconductor element and the insulation layer, removing the support body after the resin is formed to expose a surface of a portion of the conductor pattern, etching the exposed surface of the portion of the conductor pattern to form a recess over the portion of the conductor pattern, and forming a pad containing a metal different than the metal of the conductor pattern in the recess in contact with the conductor pattern.