公开(公告)号：US12113038B2

公开(公告)日：2024-10-08

申请号：US17027316

申请日：2020-09-21

Applicant: QUALCOMM Incorporated

Inventor： Dongming He ,  Hung-Yuan Hsu ,  Yangyang Sun ,  Wei Hu ,  Wei Wang ,  Lily Zhao

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/13027 ,  H01L2924/35

Abstract: A thermal compression flip chip (TCFC) bump may be used for high performance products that benefit from a fine pitch. In one example, a new TCFC bump structure adds a metal pad underneath the TCFC copper pillar bump to cover the exposed aluminum bump pad. This new structure prevents the pad from corroding and reduces mechanical stress to the pad and underlying silicon dielectric layers enabling better quality and reliability and further bump size reduction. For example, a flip chip connection may include a substrate; a metal pad on a contact side of the substrate and a first passivation layer on the contact side of the substrate to protect the metal pad from corrosion.

公开(公告)号：US09997483B2

公开(公告)日：2018-06-12

申请号：US15005461

申请日：2016-01-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsien-Wei Chen ,  Tsung-Yuan Yu ,  Wen-Hsiung Lu ,  Ming-Da Cheng

IPC: H01L21/44 ,  H01L23/00 ,  H01L23/498 ,  H01L23/31 ,  H01L23/525 ,  H01L21/56 ,  H01L21/768

CPC classification number: H01L24/13 ,  H01L21/566 ,  H01L21/76888 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/49816 ,  H01L23/525 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/02331 ,  H01L2224/02335 ,  H01L2224/02371 ,  H01L2224/0345 ,  H01L2224/03828 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05548 ,  H01L2224/05552 ,  H01L2224/05567 ,  H01L2224/05582 ,  H01L2224/05583 ,  H01L2224/05647 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/11849 ,  H01L2224/1191 ,  H01L2224/13006 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13026 ,  H01L2224/13027 ,  H01L2224/13111 ,  H01L2224/13565 ,  H01L2224/94 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01047 ,  H01L2924/01029

Abstract: An integrated circuit structure includes a semiconductor substrate, a metal pad over the semiconductor substrate, a passivation layer including a portion over the metal pad, a polymer layer over the passivation layer, and a Post-Passivation Interconnect (PPI) over the polymer layer. The PPI is electrically connected to the metal pad. The PPI includes a PPI line have a first width, and a PPI pad having a second width greater than the first width. The PPI pad is connected to the PPI line. The PPI pad includes an inner portion having a first thickness, and an edge portion having a second thickness smaller than the first thickness.

公开(公告)号：US09842775B2

公开(公告)日：2017-12-12

申请号：US15218536

申请日：2016-07-25

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Pandi C. Marimuthu ,  Shuangwu Huang ,  Nathapong Suthiwongsunthorn

IPC: H01L21/768 ,  H01L21/56 ,  H01L23/31 ,  H01L23/48 ,  H01L23/00 ,  H01L25/10 ,  H01L23/498 ,  H01L21/302 ,  H01L25/065

CPC classification number: H01L21/76898 ,  H01L21/302 ,  H01L21/56 ,  H01L21/561 ,  H01L21/76885 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/49811 ,  H01L24/02 ,  H01L24/04 ,  H01L24/05 ,  H01L24/06 ,  H01L24/10 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/02166 ,  H01L2224/02181 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05083 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/10125 ,  H01L2224/1184 ,  H01L2224/11901 ,  H01L2224/13009 ,  H01L2224/1301 ,  H01L2224/13025 ,  H01L2224/13027 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/14104 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/48 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/1058 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/182 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2224/13099 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/11849 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a conductive via in a first surface of a substrate. A first interconnect structure is formed over the first surface of the substrate. A first bump is formed over the first interconnect structure. The first bump is formed over or offset from the conductive via. An encapsulant is deposited over the first bump and first interconnect structure. A portion of the encapsulant is removed to expose the first bump. A portion of a second surface of the substrate is removed to expose the conductive via. The encapsulant provides structural support and eliminates the need for a separate carrier wafer when thinning the substrate. A second interconnect structure is formed over the second surface of the substrate. A second bump is formed over the first bump. A plurality of semiconductor devices can be stacked and electrically connected through the conductive via.

公开(公告)号：US09748191B2

公开(公告)日：2017-08-29

申请号：US15264588

申请日：2016-09-13

Applicant: Renesas Electronics Corporation

Inventor： Shinya Suzuki

IPC: H01L23/485 ,  H01L23/498 ,  H01L23/52 ,  H01L23/528 ,  H01L23/00 ,  H01L21/768 ,  H01L23/522 ,  G02F1/1345 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/311 ,  H01L27/13 ,  G02F1/133 ,  G02F1/1333 ,  G02F1/1343 ,  H01L29/78 ,  G02F1/1362 ,  G02F1/1368

CPC classification number: H01L24/14 ,  G02F1/13306 ,  G02F1/133345 ,  G02F1/134309 ,  G02F1/13439 ,  G02F1/1345 ,  G02F1/13458 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/133302 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/768 ,  H01L21/76819 ,  H01L23/485 ,  H01L23/522 ,  H01L23/528 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L27/13 ,  H01L29/7833 ,  H01L2224/02122 ,  H01L2224/0345 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05075 ,  H01L2224/051 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05553 ,  H01L2224/056 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/13005 ,  H01L2224/13006 ,  H01L2224/13009 ,  H01L2224/13013 ,  H01L2224/13022 ,  H01L2224/13027 ,  H01L2224/13144 ,  H01L2224/14153 ,  H01L2224/16225 ,  H01L2224/271 ,  H01L2224/2929 ,  H01L2224/29355 ,  H01L2224/29444 ,  H01L2224/32225 ,  H01L2224/81 ,  H01L2224/81191 ,  H01L2224/8185 ,  H01L2224/83101 ,  H01L2224/83203 ,  H01L2224/83851 ,  H01L2224/9211 ,  H01L2224/93 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1426 ,  H01L2924/15788 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2224/83 ,  H01L2924/00

Abstract: A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP.

公开(公告)号：US20170229426A1

公开(公告)日：2017-08-10

申请号：US15277349

申请日：2016-09-27

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Ching Wei HUNG ,  Wen-Jeng FAN

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/538 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L25/0657 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L23/49811 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/04 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/50 ,  H01L2021/60015 ,  H01L2021/60225 ,  H01L2224/02166 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/10126 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/13027 ,  H01L2224/19 ,  H01L2224/2101 ,  H01L2224/221 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2224/92244 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2924/3511

Abstract: Disclosed is a fan-out back-to-back chip stacked package, comprising a back-to-back stack of a first chip and a second chip, an encapsulant, a plurality of vias disposed in the encapsulant, a first redistribution layer and a second redistribution layer. The encapsulant encapsulates the sides of the first chip and the sides of the second chip simultaneously and has a thickness not greater than the chip stacked height to expose a first active surface of the first chip and a second active surface of the second chip. The encapsulant has a first peripheral surface expanding from the first active surface and a second peripheral surface expanding from the second active surface. The first redistribution layer is formed on the first active surface and extended onto the first peripheral surface to electrically connect the first chip to the vias in the encapsulant. The second RDL is formed on the second active surface and extended onto the second peripheral surface to electrically connect the second chip to the vias in the encapsulant. Accordingly, the structure realizes a thin package configuration of multi-chip back-to-back stacking to reduce package warpage.

公开(公告)号：US09659890B2

公开(公告)日：2017-05-23

申请号：US14853006

申请日：2015-09-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Wei Tu ,  Yian-Liang Kuo ,  Tsung-Fu Tsai ,  Ru-Ying Huang ,  Ming-Song Sheu ,  Hsien-Wei Chen

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/525

CPC classification number: H01L24/13 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/525 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/02375 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/0555 ,  H01L2224/05552 ,  H01L2224/0558 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/1132 ,  H01L2224/1146 ,  H01L2224/13006 ,  H01L2224/13021 ,  H01L2224/13024 ,  H01L2224/13027 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/01023 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: Methods and apparatuses for wafer level packaging (WLP) semiconductor devices are disclosed. A redistribution layer (RDL) is formed on a first passivation layer in contact with a conductive pad over a surface of a die. The RDL layer is on top of a first region of the first passivation layer. A second passivation layer is formed on the RDL layer with an opening to expose the RDL layer, and over the first passivation layer. An under bump metallization (UBM) layer is formed over the second passivation layer in contact with the exposed RDL layer. A second region of the first passivation layer disjoint from the first region is determined by projecting an outer periphery of a solder ball or other connector onto the surface.

公开(公告)号：US20170018507A1

公开(公告)日：2017-01-19

申请号：US15280632

申请日：2016-09-29

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Reza A. Pagaila ,  Flynn Carson ,  Seung Uk Yoon

IPC: H01L23/552 ,  H01L23/528 ,  H01L21/56 ,  H01L23/06 ,  H01L23/00 ,  H01L21/48 ,  H01L25/065 ,  H01L23/10

CPC classification number: H01L23/552 ,  H01L21/4871 ,  H01L21/561 ,  H01L21/568 ,  H01L23/06 ,  H01L23/10 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/5286 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/95 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/115 ,  H01L2223/6677 ,  H01L2224/02166 ,  H01L2224/0217 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13027 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/20 ,  H01L2224/215 ,  H01L2224/221 ,  H01L2224/73253 ,  H01L2224/95001 ,  H01L2224/96 ,  H01L2225/06524 ,  H01L2225/06537 ,  H01L2225/06548 ,  H01L2225/06551 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/19 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012

Abstract: A semiconductor device has a plurality of first semiconductor die mounted over an interface layer formed over a temporary carrier. An encapsulant is deposited over the first die and carrier. A flat shielding layer is formed over the encapsulant. A channel is formed through the shielding layer and encapsulant down to the interface layer. A conductive material is deposited in the channel and electrically connected to the shielding layer. The interface layer and carrier are removed. An interconnect structure is formed over conductive material, encapsulant, and first die. The conductive material is electrically connected through the interconnect structure to a ground point. The conductive material is singulated to separate the first die. A second semiconductor die can be mounted over the first die such that the shielding layer covers the second die and the conductive material surrounds the second die or the first and second die.

Abstract translation: 半导体器件具有安装在形成在临时载体上的界面层上的多个第一半导体管芯。 密封剂沉积在第一模具和载体上。 在密封剂上形成平坦的屏蔽层。 通过屏蔽层和密封剂形成通道，直到界面层。 导电材料沉积在通道中并电连接到屏蔽层。 界面层和载体被去除。 在导电材料，密封剂和第一模具上形成互连结构。 导电材料通过互连结构电连接到接地点。 将导电材料分开以分离第一模具。 可以将第二半导体管芯安装在第一管芯上，使得屏蔽层覆盖第二管芯，并且导电材料围绕第二管芯或第一和第二管芯。

公开(公告)号：US20160336230A1

公开(公告)日：2016-11-17

申请号：US15218536

申请日：2016-07-25

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Pandi C. Marimuthu ,  Shuangwu Huang ,  Nathapong Suthiwongsunthorn

IPC: H01L21/768 ,  H01L21/56 ,  H01L23/00 ,  H01L21/302 ,  H01L25/065

CPC classification number: H01L21/76898 ,  H01L21/302 ,  H01L21/56 ,  H01L21/561 ,  H01L21/76885 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/49811 ,  H01L24/02 ,  H01L24/04 ,  H01L24/05 ,  H01L24/06 ,  H01L24/10 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/02166 ,  H01L2224/02181 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05083 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/10125 ,  H01L2224/1184 ,  H01L2224/11901 ,  H01L2224/13009 ,  H01L2224/1301 ,  H01L2224/13025 ,  H01L2224/13027 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/14104 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/48 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/1058 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/182 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2224/13099 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/11849 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a conductive via in a first surface of a substrate. A first interconnect structure is formed over the first surface of the substrate. A first bump is formed over the first interconnect structure. The first bump is formed over or offset from the conductive via. An encapsulant is deposited over the first bump and first interconnect structure. A portion of the encapsulant is removed to expose the first bump. A portion of a second surface of the substrate is removed to expose the conductive via. The encapsulant provides structural support and eliminates the need for a separate carrier wafer when thinning the substrate. A second interconnect structure is formed over the second surface of the substrate. A second bump is formed over the first bump. A plurality of semiconductor devices can be stacked and electrically connected through the conductive via.

公开(公告)号：US20160268227A1

公开(公告)日：2016-09-15

申请号：US15164556

申请日：2016-05-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shang-Yun Tu ,  Yao-Chun Chuang ,  Ming Hung Tseng ,  Chen-Cheng Kuo ,  Chen-Shien Chen

IPC: H01L23/00

CPC classification number: H01L24/16 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/061 ,  H01L2224/06132 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13027 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13541 ,  H01L2224/1405 ,  H01L2224/141 ,  H01L2224/16105 ,  H01L2224/16237 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/206 ,  H01L2224/05552

Abstract: A die includes a substrate, a metal pad over the substrate, and a passivation layer covering edge portions of the metal pad. A metal pillar is formed over the metal pad. A portion of the metal pillar overlaps a portion of the metal pad. A center of the metal pillar is misaligned with a center of the metal pad.

公开(公告)号：US09379075B2

公开(公告)日：2016-06-28

申请号：US14166531

申请日：2014-01-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jie Chen ,  Hsien-Wei Chen

IPC: H01L23/48 ,  H01L23/42 ,  H01L23/00 ,  H01L21/768 ,  H01L23/485 ,  H01L23/31 ,  H01L23/525 ,  H01L23/532

CPC classification number: H01L24/13 ,  H01L21/768 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/485 ,  H01L23/525 ,  H01L23/53295 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/02255 ,  H01L2224/0231 ,  H01L2224/02333 ,  H01L2224/0235 ,  H01L2224/02351 ,  H01L2224/0236 ,  H01L2224/0239 ,  H01L2224/0382 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05555 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05649 ,  H01L2224/05655 ,  H01L2224/10145 ,  H01L2224/11015 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13027 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/059 ,  H01L2924/05994 ,  H01L2924/06 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2924/2064 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A method for manufacturing semiconductor devices is provided. In the method, a conductive pad and a metal protrusion pattern are formed in a metallization layer. A passivation layer is conformally deposited over the metallization, and a protection layer is conformally deposited over the passivation layer. Further, a post-passivation interconnect structure (PPI) is conformally formed on the protection layer, and the PPI structure includes a landing pad region, a protrusion pattern over at least a portion of the landing pad region and a connection line electrically connected to the conductive pad. A solder bump is then placed on the landing pad region in contact with the protrusion pattern of PPI structure. A to semiconductor device with bum stop structure is also provided.

Abstract translation: 提供一种半导体器件的制造方法。 在该方法中，在金属化层中形成导电焊盘和金属突起图案。 钝化层在金属化之上共形沉积，保护层共形沉积在钝化层上。 此外，钝化后互连结构（PPI）保形地形成在保护层上，并且PPI结构包括着陆焊盘区域，在着陆焊盘区域的至少一部分上的突出图案以及电连接到 导电垫。 然后将焊料凸块放置在与PPI结构的突出图案接触的着陆焊盘区域上。 还提供了具有烧结停止结构的半导体器件。