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公开(公告)号：US20210311820A1
公开(公告)日：2021-10-07
申请号：US17351619
申请日：2021-06-18
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sanguhn CHA , Hoyoung SONG , Myungkyu LEE , Sunghye CHO
IPC: G06F11/10 , G06F11/07 , G11C11/408 , G06F12/0882 , G06F13/16 , G11C11/406 , G06F11/30
Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine circuit, an error information register and a control logic circuit. The memory cell array includes memory cell rows. The control logic circuit controls the ECC engine circuit to generate an error generation signal based on performing a first ECC decoding on first sub-pages in a first memory cell row in a scrubbing operation and based on performing a second ECC decoding on second sub-pages in a second memory cell row in a normal read operation on the second memory cell row. The control logic circuit records error information in the error information register and controls the ECC engine circuit to skip an ECC encoding and an ECC decoding on a selected memory cell row of the first memory cell row and the second memory cell row based on the error information.
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2.发明申请POST PACKAGE REPAIRING METHOD, METHOD OF PREVENTING MULTIPLE ACTIVATION OF SPARE WORD LINES, AND SEMICONDUCTOR MEMORY DEVICE INCLUDING FUSE PROGRAMMING CIRCUIT 有权POST封装修复方法，防止备用字线的多重启动的方法，以及包括保险丝编程电路的半导体存储器件公开(公告)号：US20140078842A1
公开(公告)日：2014-03-20
申请号：US14030066
申请日：2013-09-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jong-min OH , Yun-young LEE , Hoyoung SONG , Chiwook KIM , Donghyun SOHN
IPC: G11C29/04
CPC classification number: G11C29/04 , G11C8/08 , G11C8/14 , G11C29/50 , G11C29/785 , G11C29/808
Abstract: Provided is a method of preventing simultaneous activation of redundancy memory line or spare word lines, the method including: programming a fail address of a memory line determined to be defective; reprogramming the fail address if a first spare line for the memory line is determined to be defective; storing additional information with respect to the reprogrammed fail address; and activating a second spare line and inactivating the first spare line, referring to the additional information.
Abstract translation: 提供了一种防止冗余存储器线或备用字线的同时激活的方法，所述方法包括：对确定为有缺陷的存储器线的故障地址进行编程; 如果存储线的第一备用线被确定为有缺陷，则重新编程故障地址; 存储关于重新编程的故障地址的附加信息; 并且参考附加信息激活第二备用线路并使第一备用线路停用。
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公开(公告)号：US20190237133A1
公开(公告)日：2019-08-01
申请号：US16379167
申请日：2019-04-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yanggyoon LOH , Hoyoung SONG , Sangwoong SHIN
IPC: G11C11/406 , G11C11/4096 , G11C11/4091 , G11C11/408 , G06F3/06
CPC classification number: G11C11/40615 , G06F3/0604 , G06F3/0659 , G06F3/0673 , G11C11/40611 , G11C11/40618 , G11C11/4087 , G11C11/4091 , G11C11/4096
Abstract: A volatile memory device includes a refresh controller configured to control a hidden refresh operation performed on a first portion of memory cells while a valid operation is performed on a second portion of the memory cells. The volatile memory device is configured to perform a regular refresh operation in response to receiving a refresh command. The refresh controller is configured to generate refresh information using a performance indicator of the hidden refresh operation during a first part of a reference time. The volatile memory device is configured to perform a desired number of the regular refresh operation during a remaining part of the reference time based on the refresh information. The desired number of the regular refresh operation is an integer based on a difference between a target number of refresh operations during the reference time and a count value of the hidden refresh operation during the reference time.
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公开(公告)号：US20180174641A1
公开(公告)日：2018-06-21
申请号：US15900070
申请日：2018-02-20
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yanggyoon LOH , Hoyoung SONG , Sangwoong SHIN
IPC: G11C11/406 , G11C11/4096 , G11C11/4091 , G11C11/408 , G06F3/06
CPC classification number: G11C11/40615 , G06F3/0604 , G06F3/0659 , G06F3/0673 , G11C11/40611 , G11C11/40618 , G11C11/4087 , G11C11/4091 , G11C11/4096
Abstract: A volatile memory device includes a refresh controller configured to control a hidden refresh operation performed on a first portion of memory cells while a valid operation is performed on a second portion of the memory cells. The volatile memory device is configured to perform a regular refresh operation in response to receiving a refresh command. The refresh controller is configured to generate refresh information using a performance indicator of the hidden refresh operation during a first part of a reference time. The volatile memory device is configured to perform a desired number of the regular refresh operation during a remaining part of the reference time based on the refresh information. The desired number of the regular refresh operation is an integer based on a difference between a target number of refresh operations during the reference time and a count value of the hidden refresh operation during the reference time.
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