公开(公告)号：US09672168B2

公开(公告)日：2017-06-06

申请号：US14320993

申请日：2014-07-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Young Hur ,  Hyun-Joon Kang ,  Sung-Min Hong

IPC: G06F13/36 ,  G06F13/16 ,  G06F13/40

CPC classification number: G06F13/1621 ,  G06F13/4022 ,  G06F13/4059

Abstract: Provided is a method of driving a system-on-chip (SOC). The method includes adding a first transaction to a list, allocating the first transaction to a first slot, determining whether a second transaction is redundant, and adding the second transaction to the list and allocating the second transaction to the first slot when it is determined that the second transaction is redundant. Accordingly, the SOC can increase outstanding capability and enhance performance of a system interconnection.

公开(公告)号：US11086388B2

公开(公告)日：2021-08-10

申请号：US15957611

申请日：2018-04-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-Joon Kang ,  Tae-Hun Kim

IPC: G06F1/3296 ,  G06F1/3234 ,  G06F1/3225

Abstract: A memory controller, an application processor, and a method of operating the memory controller can control performance and power consumption of an input/output device. The method includes allowing the memory device to enter a power down mode after an idle state is maintained for a first time period corresponding to a first setting value which is currently set, allowing the memory device to enter from the power down mode into an active state when access to the memory device occurs, determining a maintenance time of the power down mode to change the first setting value to a second setting value, based on a result obtained by monitoring a driving pattern of the memory device, and when the idle state is maintained for a second time period different from the first time period, allowing the memory device to enter the power down mode, based on the second setting value.

公开(公告)号：US09490030B2

公开(公告)日：2016-11-08

申请号：US14573379

申请日：2014-12-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-Joon Kang ,  Yongchun Kim ,  Sungkook Shin

IPC: G06F12/00 ,  G11C29/02 ,  G11C7/10 ,  G11C7/22

CPC classification number: G11C29/023 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/222 ,  G11C29/022 ,  G11C29/028

Abstract: A write leveling control method which includes registering data-related signal (DRS) reference delay values corresponding to types of memory modules in a leveling reference table; transmitting write leveling-related signals to a first type of memory module mounted on a target board; detecting timing skews between a clock signal and data-related signals received from memory devices on the mounted memory module; and adjusting a delay of a data-related signal transmitted to a memory device of the mounted memory module if a corresponding timing skew is outside of a first range, based on the DRS reference delay value corresponding to the mounted memory module.

Abstract translation: 一种写入调平控制方法，其包括在对准参考表中登记与存储器模块的类型对应的数据相关信号（DRS）参考延迟值; 将写平均相关信号发送到安装在目标板上的第一类型的存储器模块; 检测时钟信号与从所安装的存储器模块上的存储器件接收到的数据相关信号之间的时序偏差; 以及如果对应的定时偏移在第一范围之外，则基于与所安装的存储器模块对应的DRS参考延迟值，调整发送到所安装的存储器模块的存储器件的数据相关信号的延迟。