公开(公告)号：US20240113160A1

公开(公告)日：2024-04-04

申请号：US18303205

申请日：2023-04-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juseong MIN ,  Kyeonghoon PARK ,  Jae-Bok BAEK ,  Donghyuck JANG ,  Jeehoon HAN ,  Taeyoon HONG

IPC: H01L29/06 ,  H01L21/762 ,  H01L29/423

CPC classification number: H01L29/0653 ,  H01L21/76224 ,  H01L29/4236

Abstract: A semiconductor device include a substrate including a plurality of protrusions protruding from an upper surface thereof and arranged two-dimensionally in a first direction and a second direction intersecting each other, a first trench provided between the protrusions in the first direction, and a second trench provided between the protrusions in the second direction, a first device isolation layer filling the first trench, gate patterns disposed on the protrusions in the second direction, upper surfaces of the protrusions exposed at both sides of the gate patterns, respectively, and a second device isolation layer filling a space between the gate patterns in the second direction and the second trench, and each of the gate patterns has a first sidewall adjacent to the second trench and aligned with an inner wall of the second trench.

公开(公告)号：US20230039511A1

公开(公告)日：2023-02-09

申请号：US17729477

申请日：2022-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju Seong MIN ,  Jae-Bok BAEK ,  Jee Hoon HAN

IPC: H01L23/535 ,  H01L21/768 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573

Abstract: A semiconductor device includes a lower insulating film that includes a first and second trenches on a substrate, a first wiring in the first trench, a second wiring in the second trench, a capping insulating film including an insulating recess portion and an insulating liner portion, an upper insulating film on the capping insulating film, and an upper contact that penetrates the capping insulating film and connects to the first wiring, The insulating recess portion is in the second trench and the insulating liner portion extends along an upper surface of the lower insulating film. The upper contact includes a contact recess portion in the first trench, an extended portion connected to the contact recess portion, and a plug portion connected to the extended portion inside the upper insulating film. A width of the extended portion is greater than a width of the plug portion.

公开(公告)号：US20220328511A1

公开(公告)日：2022-10-13

申请号：US17541444

申请日：2021-12-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Giyong CHUNG ,  Jae-Bok BAEK ,  Jaeryong SIM ,  Jeehoon HAN

IPC: H01L27/11573 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582

Abstract: A three-dimensional semiconductor memory device includes a first substrate, a peripheral circuit structure with peripheral transistors on the first substrate, a second substrate on the peripheral circuit structure, a lower insulating layer in contact with a side surface of the second substrate, a top surface of the lower insulating layer having a concave profile, a first stack on the second substrate, the first stack including repeatedly alternating first interlayer dielectric layers and gate electrodes, and a first mold structure on the lower insulating layer, the first mold structure including repeatedly alternating sacrificial layers and second interlayer dielectric layers, and a top surface of the first mold structure being at a level lower than a topmost surface of the first stack.

公开(公告)号：US20140179096A1

公开(公告)日：2014-06-26

申请号：US14192140

申请日：2014-02-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Hwang SIM ,  Jae-Bok BAEK

IPC: H01L21/28

CPC classification number: H01L21/28 ,  H01L21/764 ,  H01L27/11529 ,  H01L27/11546 ,  H01L29/40114 ,  H01L29/7881

Abstract: A semiconductor device includes a substrate including a first region and a second region, a gate group disposed in the first region of the substrate, the gate group including a plurality of cell gate patterns and at least one selection gate pattern, a first gate pattern disposed in the second region of the substrate, a group spacer covering a top surface and a side surface of the gate group, the group spacer having a first inflection point, and a first pattern spacer covering a top surface and a side surface of the first gate pattern, the first pattern spacer having a second inflection point.

Abstract translation: 半导体器件包括：衬底，包括第一区域和第二区域;栅极组，设置在衬底的第一区域中，栅极组包括多个单元栅极图案和至少一个选择栅极图案，第一栅极图案布置 在衬底的第二区域中，覆盖栅极组的顶表面和侧表面的组间隔件，具有第一拐点的组间隔件和覆盖第一栅极的顶表面和侧表面的第一图案间隔件 第一图案间隔物具有第二拐点。