公开(公告)号：US20240130123A1

公开(公告)日：2024-04-18

申请号：US18208459

申请日：2023-06-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yejin PARK ,  Seung Yoon KIM ,  Heesuk KIM ,  Hyeongjin KIM ,  Sehee JANG ,  Minsoo SHIN ,  Seungjun SHIN ,  Sanghun CHUN ,  Jeehoon HAN ,  Jae-Hwang SIM ,  Jongseon AHN

IPC: H10B43/27 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35 ,  H10B80/00

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H01L23/5283 ,  H01L25/0652 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35 ,  H10B80/00 ,  H01L2225/06541

Abstract: Disclosed are semiconductor devices, electronic systems including the same, and methods of fabricating the same. The semiconductor device comprises a first gate stack structure including a first dielectric pattern and a first conductive pattern that are alternately stacked with each other, a memory channel structure including a first memory portion that penetrates the first gate stack structure, a through contact including a first through portion at a level the same as a level of the first memory portion, and a connection contact including a first connection portion at a level the same as the level of the first memory portion and the level of the first through portion. A minimum width of the first memory portion is less than a minimum width of the first through portion and a minimum width of the first connection portion.

公开(公告)号：US20230005955A1

公开(公告)日：2023-01-05

申请号：US17742043

申请日：2022-05-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghun CHUN ,  Kwangyoung JUNG ,  Youngji NOH ,  Junghwan PARK ,  Jeehoon HAN

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11565

Abstract: A semiconductor device includes a substrate, gate electrodes stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, channel structures penetrating the gate electrodes, extending in the first direction, and each including a channel layer, separation regions penetrating the gate electrodes, extending in the first direction and a second direction perpendicular to the first direction, and spaced apart from each other in a third direction perpendicular to the first direction and the second direction, and crack prevention layers disposed on at least a portion of the separation regions, wherein each of the separation regions includes a lower region and upper regions spaced apart from each other in the second direction on the lower region and protruding upwardly from the lower region, and wherein the crack prevention layers are in contact with upper surfaces of the upper regions.

公开(公告)号：US20250107092A1

公开(公告)日：2025-03-27

申请号：US18972118

申请日：2024-12-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghun CHUN ,  Kwangyoung JUNG ,  Youngji NOH ,  Junghwan PARK ,  Jeehoon HAN

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: A semiconductor device includes a substrate, gate electrodes stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, channel structures penetrating the gate electrodes, extending in the first direction, and each including a channel layer, separation regions penetrating the gate electrodes, extending in the first direction and a second direction perpendicular to the first direction, and spaced apart from each other in a third direction perpendicular to the first direction and the second direction, and crack prevention layers disposed on at least a portion of the separation regions, wherein each of the separation regions includes a lower region and upper regions spaced apart from each other in the second direction on the lower region and protruding upwardly from the lower region, and wherein the crack prevention layers are in contact with upper surfaces of the upper regions.

公开(公告)号：US20240284686A1

公开(公告)日：2024-08-22

申请号：US18444874

申请日：2024-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyeonghoon PARK ,  Hyunho KIM ,  Jaebok BAEK ,  Janggn YUN ,  Jeehoon HAN

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B41/27 ,  H10B43/27

CPC classification number: H10B80/00 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H10B41/27 ,  H10B43/27 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: Provided is an integrated circuit device with increased electrical reliability by forming an ohmic junction between a contact structure and a wiring line by bypassing a common source line such that the common source line, to which a common source line driver is connected, is electrically connected to the contact structure through the wiring line.

公开(公告)号：US20240260270A1

公开(公告)日：2024-08-01

申请号：US18508530

申请日：2023-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taeyoon HONG ,  Janggn YUN ,  Hyunho KIM ,  Jeehoon HAN

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B41/50 ,  H10B43/35 ,  H10B43/50

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B41/50 ,  H10B43/35 ,  H10B43/50

Abstract: A field effect transistor includes a horizontal channel layer, an interlayer insulating layer on the horizontal channel layer, a gate electrode layer on the interlayer insulating layer, a first vertical channel structure passing through the gate electrode layer and the interlayer insulating layer in a vertical direction, in contact with the horizontal channel layer, and connected to one of a source terminal or a drain terminal, and a second vertical channel structure apart from the first vertical channel structure in a horizontal direction, passing through the gate electrode layer and the interlayer insulating layer in the vertical direction, in contact with the horizontal channel layer, and connected to another of the source terminal or the drain terminal.

公开(公告)号：US20240224521A1

公开(公告)日：2024-07-04

申请号：US18428264

申请日：2024-01-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shinhwan KANG ,  Younghwan SON ,  Haemin LEE ,  Kohji KANAMORI ,  Jeehoon HAN

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/35

Abstract: A vertical semiconductor device may include a stacked structure and a plurality of channel structures. The stacked structure may include insulation layers and gate patterns alternately and repeatedly stacked on a substrate. The stacked structure may extend in a first direction parallel to an upper surface of the substrate. The gate patterns may include at least ones of first gate patterns. The stacked structure may include a sacrificial pattern between the first gate patterns. The channel structures may pass through the stacked structure. Each of the channel structures may extend to the upper surface of the substrate, and each of the channel structures may include a charge storage structure and a channel. Ones of the channel structures may pass through the sacrificial pattern in the stacked structure to the upper surface of the substrate, and may extend to the upper surface of the substrate.

公开(公告)号：US20240090228A1

公开(公告)日：2024-03-14

申请号：US18300975

申请日：2023-04-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hoyoung CHOI ,  Sanghun CHUN ,  Jeehoon HAN

IPC: H10B43/40 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

CPC classification number: H10B43/40 ,  H01L23/5226 ,  H01L23/5283 ,  H01L25/0652 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

Abstract: A semiconductor memory device comprises a first substrate, a peripheral circuit structure, and a cell array structure including a cell array region and a cell array contact region. The cell array structure includes a second substrate, a stack structure including first and second stack structures, a vertical channel structure in the cell array region, and a cell contact plug in the cell array contact region. The cell contact plug includes a first pillar part and a first protrusion part. At the level of the top surface of the first protrusion part, a first width is given as a maximum diameter at an outer perimeter of the first protrusion part. At a level of an interface between the first and second stack structures, a second width is given as a maximum width of the vertical channel structure. The first width is greater than the second width.

公开(公告)号：US20220415909A1

公开(公告)日：2022-12-29

申请号：US17903315

申请日：2022-09-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Haemin LEE ,  Jongwon KIM ,  Shinhwan KANG ,  Kohji KANAMORI ,  Jeehoon HAN

IPC: H01L27/1157 ,  H01L27/11578 ,  H01L27/11521 ,  H01L27/11556

Abstract: A semiconductor device includes a first stack group having first interlayer insulating layers and first gate layers, alternately and repeatedly stacked on a substrate and a second stack group comprising second interlayer insulating layers and second gate layers, alternately and repeatedly stacked on the first stack group. Separation structures pass through the first and second stack groups and include a first separation region and a second separation region. A vertical structure passes through the first and second stack groups and includes a first vertical region and a second vertical region. A conductive line is electrically connected to the vertical structure on the second stack group. A distance between an upper end of the first vertical region and an upper surface of the substrate is greater than a distance between an upper end of the first separation region and an upper surface of the substrate.

公开(公告)号：US20220328511A1

公开(公告)日：2022-10-13

申请号：US17541444

申请日：2021-12-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Giyong CHUNG ,  Jae-Bok BAEK ,  Jaeryong SIM ,  Jeehoon HAN

IPC: H01L27/11573 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582

Abstract: A three-dimensional semiconductor memory device includes a first substrate, a peripheral circuit structure with peripheral transistors on the first substrate, a second substrate on the peripheral circuit structure, a lower insulating layer in contact with a side surface of the second substrate, a top surface of the lower insulating layer having a concave profile, a first stack on the second substrate, the first stack including repeatedly alternating first interlayer dielectric layers and gate electrodes, and a first mold structure on the lower insulating layer, the first mold structure including repeatedly alternating sacrificial layers and second interlayer dielectric layers, and a top surface of the first mold structure being at a level lower than a topmost surface of the first stack.

公开(公告)号：US20200343259A1

公开(公告)日：2020-10-29

申请号：US16562919

申请日：2019-09-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shinhwan KANG ,  Younghwan SON ,  Haemin LEE ,  Kohji KANAMORI ,  Jeehoon HAN

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11565

Abstract: A vertical semiconductor device may include a stacked structure and a plurality of channel structures. The stacked structure may include insulation layers and gate patterns alternately and repeatedly stacked on a substrate. The stacked structure may extend in a first direction parallel to an upper surface of the substrate. The gate patterns may include at least ones of first gate patterns. The stacked structure may include a sacrificial pattern between the first gate patterns. The channel structures may pass through the stacked structure. Each of the channel structures may extend to the upper surface of the substrate, and each of the channel structures may include a charge storage structure and a channel. Ones of the channel structures may pass through the sacrificial pattern in the stacked structure to the upper surface of the substrate, and may extend to the upper surface of the substrate.