公开(公告)号：US20240134775A1

公开(公告)日：2024-04-25

申请号：US18194082

申请日：2023-03-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Eon Jo ,  Rohyoung Myung ,  Hans Gustav Åhlman

IPC: G06F11/36

CPC classification number: G06F11/3644

Abstract: An electronic device includes: one or more processors; a memory storing instructions configured to cause the one or more processors to: install instrumentation points in respective tasks of an application, the instrumentation points including a source instrumentation point installed in a source task and a target instrumentation point installed in a target task, wherein the source task and the target task are configured to execute in parallel on the one or more processors, and wherein each task includes a respective sequence of instructions executable by the one or more processors, and determine a measure of a causal relationship between the source instrumentation point and the target instrumentation point based on observation of a delay in the target instrumentation point induced by a delay amount generated by the source instrumentation point.

公开(公告)号：US12175299B2

公开(公告)日：2024-12-24

申请号：US17223139

申请日：2021-04-06

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Jae-Eon Jo ,  Hyung-Dal Kwon ,  Hanmin Park ,  Jaehyeong Sim ,  Seung Wook Lee

IPC: G06F9/50 ,  G06F1/3237 ,  G06F9/48 ,  G06N3/045 ,  G06N3/063

Abstract: A computing device and method is disclosed. The computing device includes a plurality of processing cores, and a tile scheduler configured to update a cost matrix of each of the plurality of processing cores based on meta information of each of first tiles previously allocated to the plurality of processing cores and meta information of each of second tiles, and allocate the second tiles with respect to the plurality of processing cores using the updated cost matrix of each of the plurality of processing cores.

公开(公告)号：US11960855B2

公开(公告)日：2024-04-16

申请号：US17102884

申请日：2020-11-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyung-Dal Kwon ,  Hanmin Park ,  Seungwook Lee ,  Jae-Eon Jo

IPC: G06F7/544 ,  G06F7/57 ,  G06N3/08

CPC classification number: G06F7/5443 ,  G06F7/57 ,  G06N3/08

Abstract: Disclosed is an apparatus and method for performing deep learning operations. The apparatus includes a systolic array comprising multiplier accumulator (MAC) units, and a control circuit configured to control an operation of a multiplexer connected to at least one of the MAC units and operations of the MAC units according to a plurality of operation modes.

公开(公告)号：US12130756B2

公开(公告)日：2024-10-29

申请号：US18364872

申请日：2023-08-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hanmin Park ,  Hyung-Dal Kwon ,  Jaehyeong Sim ,  Seungwook Lee ,  Jae-Eon Jo

IPC: G06F17/16 ,  G06F13/16 ,  G06N3/04

CPC classification number: G06F13/1668 ,  G06N3/04

Abstract: An accelerator, a method of operating the accelerator, and an electronic device including the accelerator. A method of operating the accelerator configured to perform a target operation includes packing input data with a data layout determined based on a word width of a memory in the accelerator and a spatial size of a filter to be applied to the target operation and storing the packed input data in the memory, and performing the target operation between a portion of the input data stored in a same word in the memory and weights of the filter.

公开(公告)号：US20240232051A9

公开(公告)日：2024-07-11

申请号：US18194082

申请日：2023-03-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Eon Jo ,  Rohyoung Myung ,  Hans Gustav Åhlman

IPC: G06F11/36

CPC classification number: G06F11/3644

Abstract: An electronic device includes: one or more processors; a memory storing instructions configured to cause the one or more processors to: install instrumentation points in respective tasks of an application, the instrumentation points including a source instrumentation point installed in a source task and a target instrumentation point installed in a target task, wherein the source task and the target task are configured to execute in parallel on the one or more processors, and wherein each task includes a respective sequence of instructions executable by the one or more processors, and determine a measure of a causal relationship between the source instrumentation point and the target instrumentation point based on observation of a delay in the target instrumentation point induced by a delay amount generated by the source instrumentation point.

公开(公告)号：US11741026B2

公开(公告)日：2023-08-29

申请号：US17182439

申请日：2021-02-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hanmin Park ,  Hyung-Dal Kwon ,  Jaehyeong Sim ,  Seungwook Lee ,  Jae-Eon Jo

IPC: G06F3/01 ,  G06F7/76 ,  G06F13/16 ,  G06N3/04

CPC classification number: G06F13/1668 ,  G06N3/04

Abstract: An accelerator, a method of operating the accelerator, and an electronic device including the accelerator. A method of operating the accelerator configured to perform a target operation includes packing input data with a data layout determined based on a word width of a memory in the accelerator and a spatial size of a filter to be applied to the target operation and storing the packed input data in the memory, and performing the target operation between a portion of the input data stored in a same word in the memory and weights of the filter.