公开(公告)号：US09875155B2

公开(公告)日：2018-01-23

申请号：US15371876

申请日：2016-12-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-soo Sohn ,  Kwang-il Park ,  Chul-woo Park ,  Jong-pil Son ,  Jae-youn Youn ,  Hoi-ju Chung

IPC: G06F11/10 ,  G06F3/06 ,  G11C29/04 ,  G11C29/12 ,  G11C29/42 ,  G11C29/44 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1052 ,  G11C29/42 ,  G11C29/44 ,  G11C29/4401 ,  G11C29/52 ,  G11C29/808 ,  G11C29/848 ,  G11C2029/0409 ,  G11C2029/0411 ,  G11C2029/1208

Abstract: Provided are a memory device and a memory module, which perform both an ECC operation and a redundancy repair operation. The memory device repairs a single-bit error due to a ‘fail’ cell by using an error correction code (ECC) operation, and also repairs the ‘fail’ cell by using a redundancy repair operation when the ‘fail’ cell is not repairable by the ECC operation. The redundancy repair operation includes a data line repair and a block repair. The ECC operation may change a codeword corresponding to data per one unit of memory cells including the ‘fail’ cell, and may also change the size of parity bits regarding the changed codeword.

公开(公告)号：US10684793B2

公开(公告)日：2020-06-16

申请号：US15462347

申请日：2017-03-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoi-ju Chung ,  Su-a Kim ,  Mu-jin Seo ,  Hak-soo Yu ,  Jae-youn Youn ,  Hyo-jin Choi

IPC: G06F11/00 ,  G06F3/06 ,  G06F11/10 ,  G06F11/07 ,  G11C11/409 ,  G11C29/00 ,  G11C29/52

Abstract: A memory controller includes a controller input/output circuit configured to output a first command to read first data, and output a second command to read an error corrected portion of the first data. A memory device includes: an error detector, a data storage circuit and an error correction circuit. The error detector is configured to detect a number of error bits in data read from a memory cell in response to a first command. The data storage circuit is configured to store the read data if the detected number of error bits is greater than or equal to a first threshold value. The error correction circuit is configured to correct the stored data.

公开(公告)号：US20170091027A1

公开(公告)日：2017-03-30

申请号：US15371876

申请日：2016-12-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-soo Sohn ,  Kwang-il Park ,  Chul-woo Park ,  Jong-pil Son ,  Jae-youn Youn ,  Hoi-ju Chung

IPC: G06F11/10 ,  G11C29/52 ,  G06F3/06

CPC classification number: G06F11/1068 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1052 ,  G11C29/42 ,  G11C29/44 ,  G11C29/4401 ,  G11C29/52 ,  G11C29/808 ,  G11C29/848 ,  G11C2029/0409 ,  G11C2029/0411 ,  G11C2029/1208

Abstract: Provided are a memory device and a memory module, which perform both an ECC operation and a redundancy repair operation. The memory device repairs a single-bit error due to a ‘fail’ cell by using an error correction code (ECC) operation, and also repairs the ‘fail’ cell by using a redundancy repair operation when the ‘fail’ cell is not repairable by the ECC operation. The redundancy repair operation includes a data line repair and a block repair. The ECC operation may change a codeword corresponding to data per one unit of memory cells including the ‘fail’ cell, and may also change the size of parity bits regarding the changed codeword.