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公开(公告)号：US10684793B2
公开(公告)日：2020-06-16
申请号：US15462347
申请日：2017-03-17
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hoi-ju Chung , Su-a Kim , Mu-jin Seo , Hak-soo Yu , Jae-youn Youn , Hyo-jin Choi
Abstract: A memory controller includes a controller input/output circuit configured to output a first command to read first data, and output a second command to read an error corrected portion of the first data. A memory device includes: an error detector, a data storage circuit and an error correction circuit. The error detector is configured to detect a number of error bits in data read from a memory cell in response to a first command. The data storage circuit is configured to store the read data if the detected number of error bits is greater than or equal to a first threshold value. The error correction circuit is configured to correct the stored data.
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Patent Agency Ranking
公开(公告)号：US09940991B2
公开(公告)日：2018-04-10
申请号：US15343977
申请日：2016-11-04
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyun-Joong Kim , Ho-young Song , Hoi-ju Chung , Ju-yun Jung , Sang-uhn Cha
IPC: G11C7/00 , G11C11/4096 , G06F3/06 , G11C7/10 , G11C11/406 , G11C29/02 , G11C29/04 , G11C29/52 , G11C29/50 , G11C29/12
CPC classification number: G11C11/4096 , G06F3/0619 , G06F3/0659 , G06F3/0673 , G11C7/1063 , G11C11/40611 , G11C11/40622 , G11C29/025 , G11C29/028 , G11C29/04 , G11C29/50016 , G11C29/52 , G11C2029/0403 , G11C2029/0409 , G11C2029/1202 , G11C2029/5002 , G11C2211/4068
Abstract: Provided are a memory device and a memory system performing request-based refresh, and an operating method of the memory device. The operating method includes: determining a weak row by counting an activated number of at least one row; requesting for refresh on the weak row based on a result of the determining; and performing target refresh on the weak row upon receiving a refresh command according to the requesting.
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3.发明申请公开(公告)号：US20170091027A1
公开(公告)日：2017-03-30
申请号：US15371876
申请日：2016-12-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Young-soo Sohn , Kwang-il Park , Chul-woo Park , Jong-pil Son , Jae-youn Youn , Hoi-ju Chung
CPC classification number: G06F11/1068 , G06F3/064 , G06F3/0679 , G06F11/1052 , G11C29/42 , G11C29/44 , G11C29/4401 , G11C29/52 , G11C29/808 , G11C29/848 , G11C2029/0409 , G11C2029/0411 , G11C2029/1208
Abstract: Provided are a memory device and a memory module, which perform both an ECC operation and a redundancy repair operation. The memory device repairs a single-bit error due to a ‘fail’ cell by using an error correction code (ECC) operation, and also repairs the ‘fail’ cell by using a redundancy repair operation when the ‘fail’ cell is not repairable by the ECC operation. The redundancy repair operation includes a data line repair and a block repair. The ECC operation may change a codeword corresponding to data per one unit of memory cells including the ‘fail’ cell, and may also change the size of parity bits regarding the changed codeword.
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公开(公告)号：US11239960B2
公开(公告)日：2022-02-01
申请号：US17079627
申请日：2020-10-26
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hoi-ju Chung , Sang-Uhn Cha , Hyun-Joong Kim
Abstract: A method of operating a semiconductor memory device can include receiving data, from a memory controller, at an Error Correction Code (ECC) engine included in the semiconductor memory device, the data including at least one predetermined error. Predetermined parity can be received at the ECC engine, where the predetermined parity is configured to correspond to the data without the at least one predetermined error. A determination can be made whether a number of errors in the data is correctable by the ECC engine using the data including the at least one predetermined error and the predetermined parity.
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公开(公告)号：US10127974B2
公开(公告)日：2018-11-13
申请号：US15909220
申请日：2018-03-01
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyun-Joong Kim , Ho-young Song , Hoi-ju Chung , Ju-yun Jung , Sang-uhn Cha
IPC: G11C7/00 , G11C11/4096 , G06F3/06 , G11C7/10 , G11C11/406 , G11C29/02 , G11C29/04 , G11C29/52 , G11C29/50 , G11C29/12
Abstract: Provided are a memory device and a memory system performing request-based refresh, and an operating method of the memory device. The operating method includes: determining a weak row by counting an activated number of at least one row; requesting for refresh on the weak row based on a result of the determining; and performing target refresh on the weak row upon receiving a refresh command according to the requesting.
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6.发明授权公开(公告)号：US09875155B2
公开(公告)日：2018-01-23
申请号：US15371876
申请日：2016-12-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Young-soo Sohn , Kwang-il Park , Chul-woo Park , Jong-pil Son , Jae-youn Youn , Hoi-ju Chung
CPC classification number: G06F11/1068 , G06F3/064 , G06F3/0679 , G06F11/1052 , G11C29/42 , G11C29/44 , G11C29/4401 , G11C29/52 , G11C29/808 , G11C29/848 , G11C2029/0409 , G11C2029/0411 , G11C2029/1208
Abstract: Provided are a memory device and a memory module, which perform both an ECC operation and a redundancy repair operation. The memory device repairs a single-bit error due to a ‘fail’ cell by using an error correction code (ECC) operation, and also repairs the ‘fail’ cell by using a redundancy repair operation when the ‘fail’ cell is not repairable by the ECC operation. The redundancy repair operation includes a data line repair and a block repair. The ECC operation may change a codeword corresponding to data per one unit of memory cells including the ‘fail’ cell, and may also change the size of parity bits regarding the changed codeword.
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