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    Memory device
    2.
    发明授权
    Memory device 有权

    公开(公告)号：US09412470B2

    公开(公告)日：2016-08-09

    申请号：US14590717

    申请日：2015-01-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jong-pil Son ,  Young-soo Sohn

    IPC: G11C29/04 ,  G11C11/408 ,  G11C29/44 ,  G11C29/00 ,  G11C17/16 ,  G11C8/00 ,  G11C16/08

    CPC classification number: G11C29/44 ,  G11C8/00 ,  G11C11/4087 ,  G11C16/08 ,  G11C17/16 ,  G11C29/04 ,  G11C29/787 ,  G11C29/808 ,  G11C2029/4402

    Abstract: A memory device including: a memory cell array including normal memory cells and spare memory cells arranged in rows and columns including normal columns including the normal memory cells and at least one spare column including spare memory cells, a segment match determining circuit configured to compare a segment address with row address information corresponding to a failed segment and to generate a load control signal, and a column match determining circuit configured to compare column address information corresponding to a failed column in response to the load control signal with a column address and to generate a column address replacement control signal, wherein the memory cells connected to fail columns of the fail segment are replaced with memory cells connected to columns of the spare memory cells in response to the column address replacement control signal.

    Memory device including error detection circuit
    3.
    发明授权
    Memory device including error detection circuit 有权

    公开(公告)号：US10460769B2

    公开(公告)日：2019-10-29

    申请号：US15681885

    申请日：2017-08-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jong-pil Son

    IPC: G11C5/04 ,  G01R31/3185 ,  G06F12/02 ,  G11C7/10 ,  G11C7/18 ,  G11C29/02 ,  G11C29/12 ,  H01L21/66 ,  H01L25/065 ,  G11C29/44 ,  G11C29/00 ,  G01R31/3187

    Abstract: A memory device includes a first memory cell array connected to a first internal data line; a second memory cell array connected to a second internal data line; and a line swap circuit configured to connect the first and second internal data lines with first and second external data lines based on an externally received driving signal. The line swap circuit is configured such that, when the driving signal has a first logic level, the line swap circuit connects the first and second internal data lines with the first and second external data lines, respectively, and when the driving signal has a second, different logic level, the line swap circuit swaps the first and second external data lines so that the first internal data line is connected to the second external data line and the second internal data line is connected to the first external data line.

    MEMORY DEVICES FOR PERFORMING MULTIPLE WRITE OPERATIONS AND OPERATING METHODS THEREOF
    4.
    发明申请
    MEMORY DEVICES FOR PERFORMING MULTIPLE WRITE OPERATIONS AND OPERATING METHODS THEREOF 审中-公开

    公开(公告)号：US20190096459A1

    公开(公告)日：2019-03-28

    申请号：US15908097

    申请日：2018-02-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jong-pil Son

    IPC: G11C8/12 ,  G11C7/10 ,  G06F3/06

    Abstract: A memory device for performing a data write operation based on a multiple write command, an operating method thereof, and an operating method of a memory controller are provided. An operating method of a memory device including a plurality of banks includes receiving a write command, and data and an address corresponding to the write command, decoding the received write command, and responsive to a result of the decoding indicating that the write command corresponds to a multiple write command, together writing the same data in two or more banks using an internal address generating operation that is based on the received address.

    MEMORY DEVICE AND CENTRAL PROCESSING UNIT
    6.
    发明申请
    MEMORY DEVICE AND CENTRAL PROCESSING UNIT 审中-公开

    公开(公告)号：US20180053535A1

    公开(公告)日：2018-02-22

    申请号：US15681885

    申请日：2017-08-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jong-pil Son

    IPC: G11C5/04 ,  G06F12/02 ,  G11C29/02 ,  G11C7/18 ,  G11C29/12 ,  G01R31/3185 ,  H01L21/66 ,  G11C7/10 ,  H01L25/065

    Abstract: A memory device includes a first memory cell array connected to a first internal data line; a second memory cell array connected to a second internal data line; and a line swap circuit configured to connect the first and second internal data lines with first and second external data lines based on an externally received driving signal. The line swap circuit is configured such that, when the driving signal has a first logic level, the line swap circuit connects the first and second internal data lines with the first and second external data lines, respectively, and when the driving signal has a second, different logic level, the line swap circuit swaps the first and second external data lines so that the first internal data line is connected to the second external data line and the second internal data line is connected to the first external data line.

    Memory device with relaxed timing parameter according to temperature, operating method thereof, and memory controller and memory system using the memory device
    8.
    发明授权
    Memory device with relaxed timing parameter according to temperature, operating method thereof, and memory controller and memory system using the memory device 有权
    具有根据温度的放松定时参数的存储器件，其操作方法以及使用存储器件的存储器控​​制器和存储器系统

    公开(公告)号：US09465757B2

    公开(公告)日：2016-10-11

    申请号：US14290997

    申请日：2014-05-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jong-pil Son ,  Uk-song Kang ,  Chul-woo Park ,  Seong-young Seo

    IPC: G06F12/02 ,  G06F13/16 ,  G11C11/406

    CPC classification number: G06F13/1689 ,  G11C7/04 ,  G11C7/1045 ,  G11C11/40626 ,  G11C11/4076

    Abstract: A memory device used with a relaxed timing requirement specification according to temperatures, an operation method thereof, and a memory controller and a memory system using the memory device are provided. The memory device has a first timing characteristic at a first temperature and a second timing characteristic that is longer than the first timing characteristic at a second temperature. If a temperature of the memory device is higher than a reference temperature, the memory controller controls the first timing characteristic as a timing requirement specification of the memory device. If the temperature of the memory device is lower than the reference temperature, the memory controller controls the second timing characteristic as the timing requirement specification of the memory device.

    Abstract translation: 提供了一种根据温度的轻松的时序要求规范使用的存储器件，其操作方法，以及使用存储器件的存储器控​​制器和存储器系统。 存储装置在第一温度下具有第一定时特性，在第二温度下具有长于第一定时特性的第二定时特性。 如果存储器件的温度高于参考温度，则存储器控制器控制第一定时特性作为存储器件的定时要求指定。 如果存储器件的温度低于参考温度，则存储器控制器控制第二定时特性作为存储器件的定时要求规范。

    MEMORY DEVICE WITH RELAXED TIMING PARAMETER ACCORDING TO TEMPERATURE, OPERATING METHOD THEREOF, AND MEMORY CONTROLLER AND MEMORY SYSTEM USING THE MEMORY DEVICE
    9.
    发明申请
    MEMORY DEVICE WITH RELAXED TIMING PARAMETER ACCORDING TO TEMPERATURE, OPERATING METHOD THEREOF, AND MEMORY CONTROLLER AND MEMORY SYSTEM USING THE MEMORY DEVICE 有权
    具有根据温度的放松时序参数的存储器件，其操作方法，以及使用存储器件的存储器控​​制器和存储器系统

    公开(公告)号：US20140359242A1

    公开(公告)日：2014-12-04

    申请号：US14290997

    申请日：2014-05-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jong-pil Son ,  Uk-song Kang ,  Chul-woo Park ,  Seong-young Seo

    IPC: G06F13/16

    CPC classification number: G06F13/1689 ,  G11C7/04 ,  G11C7/1045 ,  G11C11/40626 ,  G11C11/4076

    Abstract: A memory device used with a relaxed timing requirement specification according to temperatures, an operation method thereof, and a memory controller and a memory system using the memory device are provided. The memory device has a first timing characteristic at a first temperature and a second timing characteristic that is longer than the first timing characteristic at a second temperature. If a temperature of the memory device is higher than a reference temperature, the memory controller controls the first timing characteristic as a timing requirement specification of the memory device. If the temperature of the memory device is lower than the reference temperature, the memory controller controls the second timing characteristic as the timing requirement specification of the memory device.

    Abstract translation: 提供了一种根据温度的轻松的时序要求规范使用的存储器件，其操作方法，以及使用存储器件的存储器控​​制器和存储器系统。 存储装置在第一温度下具有第一定时特性，在第二温度下具有长于第一定时特性的第二定时特性。 如果存储器件的温度高于参考温度，则存储器控制器控制第一定时特性作为存储器件的定时要求指定。 如果存储器件的温度低于参考温度，则存储器控制器控制第二定时特性作为存储器件的定时要求规范。

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