公开(公告)号：US20240304557A1

公开(公告)日：2024-09-12

申请号：US18479820

申请日：2023-10-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyujin CHOI ,  Dahee KIM ,  Jaeean LEE ,  Taehoon LEE

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/552 ,  H01L25/065

CPC classification number: H01L23/5383 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/552 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0652 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/13 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/73204

Abstract: A semiconductor package includes a first redistribution structure in which at least one first redistribution layer and at least one first insulating layer are alternately layered; a first semiconductor chip disposed on an upper surface of the first redistribution structure; a second semiconductor chip having a lower portion surrounded by the first redistribution structure; a first encapsulant disposed on the upper surface of the first redistribution structure to encapsulate the first semiconductor chip; a second encapsulant encapsulating the second semiconductor chip and having a lower portion surrounded by the first redistribution structure; and a conductive support layer supporting the second semiconductor chip and the second encapsulant on an upper surface of the second semiconductor chip.

公开(公告)号：US20220165693A1

公开(公告)日：2022-05-26

申请号：US17343992

申请日：2021-06-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeean LEE ,  Changeun JOO ,  Gyujin CHOI

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: A semiconductor package including a semiconductor chip; a lower redistribution layer on a lower surface of the semiconductor chip; a lower passivation layer on a lower surface of the lower redistribution layer; a UBM pad on the lower passivation layer and including an upper pad and a lower pad connected to the upper pad, the upper pad having a greater horizontal length at an upper surface thereof than a horizontal length at a lower surface thereof; a seed layer between the lower passivation layer and the UBM pad; and an external connecting terminal on a lower surface of the UBM pad, wherein the seed layer includes a first seed part covering a side surface of the upper pad, a second seed part covering a portion of the lower surface of the upper pad, and a third seed part covering a portion of a side surface of the lower pad.

公开(公告)号：US20250015043A1

公开(公告)日：2025-01-09

申请号：US18748295

申请日：2024-06-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeean LEE ,  Dongwon KANG ,  Changyeon SONG ,  Sunguk LEE

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498

Abstract: A semiconductor package includes: a first redistribution structure including a first upper connection pad and a first lower connection pad; a first semiconductor device on the first redistribution structure; a vertical connection conductor on the first redistribution structure; an encapsulant adjacent to the first semiconductor device; a second redistribution structure on the encapsulant and including a second redistribution pattern, a second insulating layer, a second upper connection pad, and a second lower connection pad; an insulating adhesive layer between the second redistribution structure and the encapsulant; and an intermediate connection terminal connecting the second lower connection pad with the vertical connection conductor, wherein the second upper connection pad is exposed by an upper opening of the second insulating layer. A cover conductive layer is on the second upper connection pad. A side surface of the intermediate connection terminal is covered with the insulating adhesive layer and the encapsulant.

公开(公告)号：US20210183756A1

公开(公告)日：2021-06-17

申请号：US16991306

申请日：2020-08-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seunghun CHAE ,  Youngkwan SEO ,  Jaeean LEE ,  Soyeon MOON ,  Hyeyeong JO ,  Iljong SEO

IPC: H01L23/498 ,  H01L25/065 ,  H01L23/00 ,  H01L23/367 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor package includes a redistribution substrate having first and second surfaces, and an insulating member and a plurality of redistribution layers on different levels in the insulating member and electrically connected together; a plurality of under bump metallurgy (UBM) pads in the insulating member and connected to a redistribution layer, among the plurality of redistribution layers, adjacent to the first surface, the UBM pads having a lower surface exposed to the first surface of the redistribution substrate; a dummy pattern between the UBM pads in the insulating member, the dummy pattern having a lower surface located at a level higher than the lower surface of the UBM pads; and at least one semiconductor chip on the second surface of the redistribution substrate and having a plurality of contact pads electrically connected to a redistribution layer, among the plurality of redistribution layers, adjacent to the second surface.

公开(公告)号：US20250079317A1

公开(公告)日：2025-03-06

申请号：US18813120

申请日：2024-08-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changyeon SONG ,  Dongwon KANG ,  Sunguk LEE ,  Jaeean LEE ,  Gyujin CHOI

IPC: H01L23/532 ,  H01L23/14 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor package according to an embodiment includes a first substrate having an upper surface and a lower surface and a cavity extending from the upper surface to the lower surface; a first chip mounted in the cavity; a first redistribution structure disposed on the first chip; a passive element mounted inside the first redistribution structure; and an adhesive layer disposed below the passive element. The first redistribution structure includes a plurality of redistribution insulating layers stacked in a vertical direction on the first chip, and a first redistribution pattern and a second redistribution pattern located within the redistribution insulating layers. The first redistribution pattern is disposed below a recess vertically penetrating at least one redistribution insulating layer among the plurality of redistribution insulating layers. The second redistribution pattern is adjacent to the recess in a lateral direction.

公开(公告)号：US20220384329A1

公开(公告)日：2022-12-01

申请号：US17885664

申请日：2022-08-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seunghun CHAE ,  Youngkwan SEO ,  Jaeean LEE ,  Soyeon MOON ,  Hyeyeong JO ,  Iljong SEO

IPC: H01L23/498 ,  H01L25/065 ,  H01L23/00 ,  H01L23/367 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor package includes a redistribution substrate having first and second surfaces, and an insulating member and a plurality of redistribution layers on different levels in the insulating member and electrically connected together; a plurality of under bump metallurgy (UBM) pads in the insulating member and connected to a redistribution layer, among the plurality of redistribution layers, adjacent to the first surface, the UBM pads having a lower surface exposed to the first surface of the redistribution substrate; a dummy pattern between the UBM pads in the insulating member, the dummy pattern having a lower surface located at a level higher than the lower surface of the UBM pads; and at least one semiconductor chip on the second surface of the redistribution substrate and having a plurality of contact pads electrically connected to a redistribution layer, among the plurality of redistribution layers, adjacent to the second surface.

公开(公告)号：US20210366878A1

公开(公告)日：2021-11-25

申请号：US17392511

申请日：2021-08-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungsoo BYUN ,  Taesung JEONG ,  Younggwan KO ,  Jaeean LEE

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00

Abstract: A semiconductor package includes an interposer, first and second semiconductor chips, and electrical connection structures. The interposer includes a first connection structure having a first redistribution conductor, second connection structures each having a second redistribution conductor, third connection structures each having a third redistribution conductor, and a passivation layer filling spaces between the first to third connection structures. The first semiconductor chip is disposed on the interposer to overlap the first connection structure and some third connection structures. The second semiconductor chip is disposed on the interposer to overlap some second connection structures and third connection structures. The electrical connection structures are electrically connected to the first and second chips. The first redistribution conductor electrically connects the first chip to some electrical connection structures, the second redistribution conductor electrically connects the second chip to some electrical connection structures, and the third redistribution conductor electrically connects the first and second chips.