公开(公告)号：US20210183756A1

公开(公告)日：2021-06-17

申请号：US16991306

申请日：2020-08-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seunghun CHAE ,  Youngkwan SEO ,  Jaeean LEE ,  Soyeon MOON ,  Hyeyeong JO ,  Iljong SEO

IPC: H01L23/498 ,  H01L25/065 ,  H01L23/00 ,  H01L23/367 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor package includes a redistribution substrate having first and second surfaces, and an insulating member and a plurality of redistribution layers on different levels in the insulating member and electrically connected together; a plurality of under bump metallurgy (UBM) pads in the insulating member and connected to a redistribution layer, among the plurality of redistribution layers, adjacent to the first surface, the UBM pads having a lower surface exposed to the first surface of the redistribution substrate; a dummy pattern between the UBM pads in the insulating member, the dummy pattern having a lower surface located at a level higher than the lower surface of the UBM pads; and at least one semiconductor chip on the second surface of the redistribution substrate and having a plurality of contact pads electrically connected to a redistribution layer, among the plurality of redistribution layers, adjacent to the second surface.

公开(公告)号：US20240105536A1

公开(公告)日：2024-03-28

申请号：US18369474

申请日：2023-09-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seokbong PARK ,  Sechul PARK ,  Unbyoung KANG ,  Junhyun AN ,  Hyojin YUN ,  Seunghun CHAE

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/498 ,  H01L25/10

CPC classification number: H01L23/3107 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49866 ,  H01L24/16 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2924/15174

Abstract: A semiconductor package includes a first redistribution structure, a first semiconductor chip on the first redistribution structure, a first molding layer on the first redistribution structure, the first molding layer including at least one lower recess in a top surface thereof and being disposed on the first semiconductor chip, connection structures on the first redistribution structure, the connection structures extending in a vertical direction and passing through the first molding layer, a first insulating layer on the first molding layer, and a second redistribution structure including a lower redistribution insulating layer on the first insulating layer, wherein the first insulating layer at least partially fills the at least one lower recess of the first molding layer.

公开(公告)号：US20220384329A1

公开(公告)日：2022-12-01

申请号：US17885664

申请日：2022-08-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seunghun CHAE ,  Youngkwan SEO ,  Jaeean LEE ,  Soyeon MOON ,  Hyeyeong JO ,  Iljong SEO

IPC: H01L23/498 ,  H01L25/065 ,  H01L23/00 ,  H01L23/367 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor package includes a redistribution substrate having first and second surfaces, and an insulating member and a plurality of redistribution layers on different levels in the insulating member and electrically connected together; a plurality of under bump metallurgy (UBM) pads in the insulating member and connected to a redistribution layer, among the plurality of redistribution layers, adjacent to the first surface, the UBM pads having a lower surface exposed to the first surface of the redistribution substrate; a dummy pattern between the UBM pads in the insulating member, the dummy pattern having a lower surface located at a level higher than the lower surface of the UBM pads; and at least one semiconductor chip on the second surface of the redistribution substrate and having a plurality of contact pads electrically connected to a redistribution layer, among the plurality of redistribution layers, adjacent to the second surface.