公开(公告)号：US20210035991A1

公开(公告)日：2021-02-04

申请号：US16827778

申请日：2020-03-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihye KIM ,  Jaehoon LEE ,  Jiyoung KIM ,  Bongtae PARK ,  Jaejoo SHIM

IPC: H01L27/112 ,  H01L27/32 ,  H01L27/11585

Abstract: A semiconductor device includes a substrate having a conductive region and an insulating region; gate electrodes including sub-gate electrodes spaced apart from each other and stacked in a first direction perpendicular to an upper surface of the substrate and extending in a second direction perpendicular to the first direction and gate connectors connecting the sub-gate electrodes disposed on the same level; channel structures penetrating through the gate electrodes and extending in the conductive region of the substrate; and a first dummy channel structure penetrating through the gate electrodes and extending in the insulating region of the substrate and disposed adjacent to at least one side of the gate connectors in a third direction perpendicular to the first and second directions.

公开(公告)号：US20220149056A1

公开(公告)日：2022-05-12

申请号：US17580811

申请日：2022-01-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihye KIM ,  Jaehoon LEE ,  Jiyoung KIM ,  Bongtae PARK ,  Jaejoo SHIM

IPC: H01L27/112 ,  H01L27/11585 ,  H01L27/32 ,  H01L27/108 ,  H01L29/49

Abstract: A semiconductor device includes a substrate having a conductive region and an insulating region; gate electrodes including sub-gate electrodes spaced apart from each other and stacked in a first direction perpendicular to an upper surface of the substrate and extending in a second direction perpendicular to the first direction and gate connectors connecting the sub-gate electrodes disposed on the same level; channel structures penetrating through the gate electrodes and extending in the conductive region of the substrate; and a first dummy channel structure penetrating through the gate electrodes and extending in the insulating region of the substrate and disposed adjacent to at least one side of the gate connectors in a third direction perpendicular to the first and second directions.

公开(公告)号：US20240315021A1

公开(公告)日：2024-09-19

申请号：US18183469

申请日：2023-03-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Siwan KIM ,  Juwon IM ,  Jonghyun PARK ,  Sori LEE ,  Bongtae PARK ,  Jaejoo SHIM

IPC: H10B43/27 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: A semiconductor device includes a first semiconductor structure including a first substrate and circuit devices; and a second semiconductor structure including a second substrate on the first semiconductor structure and having a first region and a second region, gate electrodes in the first region and stacked in a first direction, and extending in the second region by different lengths in a second direction, channel structures extending by penetrating through the gate electrodes, separation regions penetrating through the gate electrodes, extending in the second direction, spaced apart from each other in a third direction, and defining a center block region and an edge block region, and substrate insulating layers in the second substrate between the separation regions in the second region. A width of the substrate insulating layers in the third direction is greater in the edge block region than in the center block region.

公开(公告)号：US20230026774A1

公开(公告)日：2023-01-26

申请号：US17709803

申请日：2022-03-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungmin HWANG ,  Taewon KANG ,  Dongsung WOO ,  Taegon LEE ,  Bongtae PARK ,  Jaejoo SHIM

IPC: H01L27/108

Abstract: A semiconductor device and a data storage system including the same, the semiconductor device including a substrate structure; a stack structure; a vertical memory structure; a vertical dummy structure; and an upper separation pattern, wherein hen viewed on a plane at a first height level, higher than a height level of a lowermost end of the upper separation pattern, the dummy channel layer includes a first dummy channel region facing the dummy data storage layer and a second dummy channel region facing the dummy data storage layer, the first dummy channel region having a thickness different from a thickness of the second dummy channel region.