公开(公告)号：US20240268113A1

公开(公告)日：2024-08-08

申请号：US18229560

申请日：2023-08-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghun CHUN ,  Jaehoon LEE ,  Kyung Taek CHO ,  Donghyuck JANG ,  Jeehoon HAN

IPC: H10B43/27 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B43/40

Abstract: A semiconductor device includes a circuit region, a peripheral circuit structure on a first substrate; a cell region on the circuit region, a cell array region and connection region, the cell region including a second substrate; gate stacking structure on the second substrate, a lower structure, upper structures including gate electrodes; a channel structure penetrating the gate stacking structure; a gate contact penetrating the gate stacking structure electrically connected to the circuit region, and to a connection gate electrode insulated from a gate electrode by an insulating pattern between the gate electrode and the gate contact; a boundary insulating pattern partially formed in a boundary gate electrode among the gate electrodes of the lower structure adjacent to a boundary portion between the upper and lower structure surrounding the gate contact to maintain an electrical connection path of the boundary gate electrode and having a different structure from the insulating pattern.

公开(公告)号：US20220149056A1

公开(公告)日：2022-05-12

申请号：US17580811

申请日：2022-01-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihye KIM ,  Jaehoon LEE ,  Jiyoung KIM ,  Bongtae PARK ,  Jaejoo SHIM

IPC: H01L27/112 ,  H01L27/11585 ,  H01L27/32 ,  H01L27/108 ,  H01L29/49

Abstract: A semiconductor device includes a substrate having a conductive region and an insulating region; gate electrodes including sub-gate electrodes spaced apart from each other and stacked in a first direction perpendicular to an upper surface of the substrate and extending in a second direction perpendicular to the first direction and gate connectors connecting the sub-gate electrodes disposed on the same level; channel structures penetrating through the gate electrodes and extending in the conductive region of the substrate; and a first dummy channel structure penetrating through the gate electrodes and extending in the insulating region of the substrate and disposed adjacent to at least one side of the gate connectors in a third direction perpendicular to the first and second directions.

公开(公告)号：US20220113889A1

公开(公告)日：2022-04-14

申请号：US17337992

申请日：2021-06-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaewon PARK ,  Sangkil PARK ,  Jaehoon LEE

IPC: G06F3/06

Abstract: A method of testing a memory device, a memory built-in self-test (MBIST) circuit, and a memory device for improving reliability and reducing a test time. The memory device includes a plurality of memory banks and the MBIST circuit. The MBIST circuit is configured to generate double data rate (DDR) test patterns and parallel bit test (PBT) test patterns to test the memory banks. When a defective cell is detected as a result of the PBT test or the DDR test, the MBIST circuit is configured to perform a repair operation for replacing the defective cell with a redundancy cell and perform a re-test to verify the repair operation. The MBIST circuit may be configured to perform the DDR test on one or more memory cells including the defective cell during the re-test.

公开(公告)号：US20230413443A1

公开(公告)日：2023-12-21

申请号：US18230444

申请日：2023-08-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Younghun SEONG ,  Bumhee BAE ,  Euisung KANG ,  Hyeonhak KIM ,  Kanghyun RYOO ,  Jaehoon LEE

IPC: H05K1/14 ,  G06F1/16 ,  H05K1/11 ,  H05K1/02

CPC classification number: H05K1/147 ,  H05K1/028 ,  H05K1/118 ,  G06F1/1652

Abstract: An electronic device can include a hinge structure; a flexible display which is folded or unfolded by the hinge structure; a first portion and a second portion which are close to and facing each other when folded by the hinge structure, and spaced apart when unfolded; a first circuit board disposed on the first portion; a second circuit board disposed on the second portion; and a flexible circuit board electrically connecting the first printed circuit board and the second circuit board. The flexible printed circuit board includes a first area which bends in response to the deformation of the electronic device, and a second region positioned around the first region that does not bend. The first region may include a single main signal wiring layer. The second portion may include a plurality of signal wiring layers. The first region and the second region may be formed to have different thicknesses.

公开(公告)号：US20220407459A1

公开(公告)日：2022-12-22

申请号：US17845378

申请日：2022-06-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehong JUNG ,  Seunghyun OH ,  Jinhyeon LEE ,  Gihyeok HA ,  Seungjin KIM ,  Joomyoung KIM ,  Yelim YOUN ,  Jaehoon LEE

IPC: H03B5/32 ,  H03B5/20 ,  H03B5/04 ,  G06F1/06

Abstract: A clock integrated circuit is provided. The clock integrated circuit includes: a first clock generator which includes a crystal oscillator configured to generate a first clock signal; and a second clock generator which includes a resistance-capacitance (RC) oscillator and a first frequency divider, and is configured to: generate a second clock signal using the first frequency divider based on a clock signal output from the RC oscillator; perform a first calibration operation for adjusting a frequency division ratio of the first frequency divider to a first frequency division ratio based on the first clock signal; and perform a second calibration operation for adjusting the first frequency division ratio to a second frequency division ratio based on a sensed temperature.

公开(公告)号：US20170317083A1

公开(公告)日：2017-11-02

申请号：US15652386

申请日：2017-07-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehoon LEE

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/10 ,  H01L29/778 ,  H01L29/267 ,  H01L29/423 ,  H01L29/20 ,  H01L21/8258

CPC classification number: H01L27/0922 ,  H01L21/8258 ,  H01L29/1054 ,  H01L29/2003 ,  H01L29/267 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7786

Abstract: A semiconductor device is provided as follows. A first buffer layer is disposed on a substrate including NMOS and PMOS regions. A first drain and a first source are disposed on the first buffer layer and have heterogeneous structures. A first channel is disposed between the first drain and the first source. A first gate electrode is disposed on the first channel. A second drain and a second source are disposed on the first buffer layer. A second channel is disposed between the second drain and the second source. The second channel includes a different material from the first channel. A second gate electrode is disposed on the second channel. The first drain, the first source, the first channel and the first gate electrode are disposed in the NMOS region. The second drain, the second source, the second channel and the second gate electrode are disposed in the PMOS region.

公开(公告)号：US20230171881A1

公开(公告)日：2023-06-01

申请号：US18096844

申请日：2023-01-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bumhee BAE ,  Younghun SEONG ,  Jaehoon LEE ,  Jeongnam CHEON

IPC: H05K1/02 ,  H05K1/18

CPC classification number: H05K1/028 ,  H05K1/0272 ,  H05K1/181 ,  H05K2201/09063 ,  H05K2201/093 ,  H05K2201/10128 ,  H05K2201/10098 ,  G06F1/1652

Abstract: A flexible printed circuit board (FPCB) assembly includes an electrically conductive layer configured to transmit a signal, a dielectric layer provided on the electrically conductive layer, a ground layer provided on the dielectric layer, and an auxiliary metal layer provided on or under the ground layer, and connecting a plurality of regions of the ground layer to each other, where the electrically conductive layer, the dielectric layer, the ground layer, and the auxiliary metal layer are flexible.

公开(公告)号：US20230050589A1

公开(公告)日：2023-02-16

申请号：US17883860

申请日：2022-08-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehyeok LEE ,  Taikuin MUN ,  Jaehoon LEE

IPC: H04W76/14 ,  H04W76/11 ,  H04W4/80 ,  H04W76/18

Abstract: Electronic devices are disclosed herein. Each device includes a display, communication circuitry and a processor. For each device, the respective processor executes registering a geographic locale indicator for the electronic device via a universally unique identified (UUID), equipment identity register (EIR) or manufacturer information. For a first device, a setup mode is executed, including transmitting the UUID, EIR, or manufacturer information to a second device, which may then determine is communication is possible with the first device based on the geographic locale indicator. The first device may receive a response indicative of whether the locales between the devices match. Based on the same, the first and/or second device may also display an indication as to whether communication is possible with the second device.

公开(公告)号：US20210035991A1

公开(公告)日：2021-02-04

申请号：US16827778

申请日：2020-03-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihye KIM ,  Jaehoon LEE ,  Jiyoung KIM ,  Bongtae PARK ,  Jaejoo SHIM

IPC: H01L27/112 ,  H01L27/32 ,  H01L27/11585

Abstract: A semiconductor device includes a substrate having a conductive region and an insulating region; gate electrodes including sub-gate electrodes spaced apart from each other and stacked in a first direction perpendicular to an upper surface of the substrate and extending in a second direction perpendicular to the first direction and gate connectors connecting the sub-gate electrodes disposed on the same level; channel structures penetrating through the gate electrodes and extending in the conductive region of the substrate; and a first dummy channel structure penetrating through the gate electrodes and extending in the insulating region of the substrate and disposed adjacent to at least one side of the gate connectors in a third direction perpendicular to the first and second directions.

公开(公告)号：US20200052922A1

公开(公告)日：2020-02-13

申请号：US16535683

申请日：2019-08-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehyeok LEE ,  Taikuin MUN ,  Jaehoon LEE ,  Jongkeun CHOI

IPC: H04L12/18 ,  H04L12/28 ,  H04L12/58

Abstract: An electronic device includes a display, communication circuitry performing wireless connection with an external electronic device, a processor operatively coupled with the display and the communication circuitry, and a memory operatively connected with the processor. Based on executing instructions stored in the memory, the processor is configured to control the electronic device to receive information on a first notification message generated within the external electronic device using the communication circuitry. Based on instructions stored in the memory being executed, the processor controls the electronic device to display the first notification message through the display. Based on the instructions stored in the memory being executed, the processor is configured to control the electronic device to receive one or more second notification messages which have been generated within the external electronic device prior to the first notification message. Based on instructions stored in the memory being executed, the processor is configured to control the electronic device to display, in response to an input, the second notification message in at least a portion of the display.