公开(公告)号：US20230005838A1

公开(公告)日：2023-01-05

申请号：US17672990

申请日：2022-02-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaemyung CHOI ,  Kyoungwoo LEE ,  Nayon KIM ,  Seonghun LIM ,  Sungyup JUNG

IPC: H01L23/522 ,  H01L21/033 ,  H01L21/768 ,  H01L23/528

Abstract: A semiconductor device includes a lower structure, a first interlayer dielectric (ILD) on the lower structure, first pattern regions extending inside the first ILD in a first direction, the first pattern regions being spaced apart from each other in a second direction perpendicular to the first direction, each of the first pattern regions including at least one first pattern, and both ends of the at least one first pattern in the first direction being concave, and second pattern regions extending inside the first ILD in the first direction, the second pattern regions being spaced apart from each other in the second direction and alternating with the first pattern regions in the second direction, and each of the second pattern regions including at least one second pattern.

公开(公告)号：US20250022797A1

公开(公告)日：2025-01-16

申请号：US18378789

申请日：2023-10-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaemyung CHOI ,  Janggeun LEE ,  Wonhyuk HONG ,  Kang-ill SEO

IPC: H01L23/528 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A semiconductor device includes: a frontside structure including at least one of a front-end-of-line (FEOL) structure, a middle-of-line (MOL) structure, and a back-end-of-line (BEOL) structure; a 1st metal line on the frontside structure; and a 2nd metal line on the frontside structure, wherein the 1st metal line has a greater width than the 2nd metal line in a same direction, and the 1st metal line and the 2nd metal line have an equal height.

公开(公告)号：US20250167106A1

公开(公告)日：2025-05-22

申请号：US18738802

申请日：2024-06-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaemyung CHOI ,  Kang-ill SEO

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: Provided is a semiconductor device which includes: a base layer including at least one transistor structure; and an interconnect structure above the base layer in a 3rd direction, wherein the interconnect structure includes a 1st metal line, a 2nd metal line, and at least one another metal line extended in a 1st direction and arranged at a 2nd direction, wherein at least a 1st portion of the 1st metal line having a 1st metal-to-metal distance to at least a portion of another metal line adjacent thereto in the 2nd direction has a greater height than at least a 1st portion of the 2nd metal line having a 2nd metal-to-metal distance to at least a portion of another metal line adjacent thereto in the 2nd direction, wherein the 1st metal-to-metal distance is greater than the 2nd metal-to-metal distance, and wherein the 1st direction and the 2nd direction horizontally intersect each other, and vertically intersect the 3rd direction.

公开(公告)号：US20230343697A1

公开(公告)日：2023-10-26

申请号：US17841245

申请日：2022-06-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Janggeun LEE ,  Jaemyung CHOI ,  Kang-ill SEO

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877

Abstract: A connection structure for an integrated circuit includes: a 1st layer including a 1st metal line; a 2nd layer, above the 1st layer, including a 1st via; and a 3rd layer, above the 2nd layer, including a 2nd metal line connected to the 1st metal line through the 1st via, wherein the 1st via comprises a spacer structure at a side of an upper portion of the 1st via, the spacer structure comprising an insulation material.

公开(公告)号：US20250125253A1

公开(公告)日：2025-04-17

申请号：US18618469

申请日：2024-03-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joongsuk OH ,  Jaemyung CHOI ,  Kang-ill SEO

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: Provided is a semiconductor device which includes: a transistor structure; a plurality of 1st metal lines above the transistor structure; and a plurality of 1st vias formed on selected 1st metal lines, respectively, among the plurality of 1st metal lines; a 2nd via formed on a 1st via among the plurality of 1st vias; and a 2nd metal line on the 2nd via, wherein the 1st metal lines are arranged in a 1st direction and extended in a 2nd direction which intersects the 1st direction, and the 2nd metal line is extended in the 1st direction, and wherein the plurality of 1st vias comprise at least one dummy via which is not connected to any metal line thereabove other than an underlying 1st metal line among the selected 1st metal lines.

公开(公告)号：US20230343698A1

公开(公告)日：2023-10-26

申请号：US17883073

申请日：2022-08-08

Applicant: SAMSUNG ELECTRONICS CO, LTD.

Inventor： Jaemyung CHOI ,  Tae Sun KIM ,  Janggeun LEE ,  Kang-ill SEO

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76834 ,  H01L21/76832 ,  H01L21/76807 ,  H01L23/53295

Abstract: Provided is a semiconductor device including at least one front-end-of-line (FEOL) element connected to an interconnect structure, the interconnect structure including: a 1st metal pattern or via structure with a spacer structure on a sidewall thereof; and a 1st interlayer dielectric (ILD) layer formed at sides of the 1st metal pattern or via structure with the spacer structure on the sidewall thereof, wherein the spacer structure includes a dielectric material different from a material included in the 1st ILD layer.

公开(公告)号：US20220270890A1

公开(公告)日：2022-08-25

申请号：US17395030

申请日：2021-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaemyung CHOI ,  Kyoungwoo LEE

IPC: H01L21/3213 ,  H01L21/027

Abstract: A method for manufacturing a semiconductor device including forming an insulating structure, forming a hard mask layer on the insulating structure, performing a first etching process to form a first opening at the hard mask layer, forming a first sacrificial pattern in the first opening, forming, on the hard mask layer, a first photoresist pattern including a second opening and a third opening, the second opening exposing a top surface of the first sacrificial pattern, the third opening exposing a top surface of the hard mask layer, and performing a second etching process using the first photoresist pattern as an etch mask may be provided.