PARALLELIZATION METHOD AND APPARATUS WITH PROCESSING OF NEURAL NETWORK MODEL FOR MANYCORE SYSTEM

    公开(公告)号:US20220129325A1

    公开(公告)日:2022-04-28

    申请号:US17224428

    申请日:2021-04-07

    Inventor: Jaeyeon KIM

    Abstract: A parallelization method includes: generating a profiling result by performing profiling on a target neural network based on model information of the target neural network and architecture information of a manycore system; determining an assignment strategy to assign a plurality of cores of each of a plurality of clusters of the manycore system to a plurality of layers of the target neural network, based on the profiling result; and generating a parallelization strategy for parallel processing of the manycore system based on the assignment strategy.

    MEMORY DEVICES
    2.
    发明公开
    MEMORY DEVICES 审中-公开

    公开(公告)号:US20240188305A1

    公开(公告)日:2024-06-06

    申请号:US18526031

    申请日:2023-12-01

    CPC classification number: H10B63/22 H10B63/10 H10B63/80

    Abstract: A memory device includes a substrate; a plurality of first conductive lines on the substrate and extending in a first direction; a plurality of second conductive lines on the plurality of first conductive lines and extending in a second direction crossing the first direction; and a plurality of first memory cells respectively arranged between the plurality of first conductive lines and the plurality of second conductive lines, wherein each first memory cell of the plurality of first memory cells includes a switching device and a variable resistance material pattern, and the switching device includes a material having a composition of LaxNi1-xOy, in which 0.13≤x≤0.30 and 0.9≤y≤1.5.

    PARALLEL PROCESSING METHOD AND APPARATUS FOR NEUTRAL NETWORK MODEL

    公开(公告)号:US20210287085A1

    公开(公告)日:2021-09-16

    申请号:US17023496

    申请日:2020-09-17

    Inventor: Jaeyeon KIM

    Abstract: A parallel processing method and apparatus for a neural network model. The parallel processing method includes extracting metadata of a target layer included in a target model, measuring a similarity between the target layer and each of reference layers by comparing the metadata of the target layer to reference metadata of each of the reference layers, selecting a corresponding layer among the reference layers based on the similarities, and generating a parallelization strategy for the target layer based on a reference parallelization strategy matching the corresponding layer.

    DISPLAY DRIVING INTEGRATED CIRCUIT AND DISPLAY DEVICE INCLUDING THE SAME
    5.
    发明申请
    DISPLAY DRIVING INTEGRATED CIRCUIT AND DISPLAY DEVICE INCLUDING THE SAME 有权
    显示驱动集成电路和显示装置,包括它们

    公开(公告)号:US20160260409A1

    公开(公告)日:2016-09-08

    申请号:US14972435

    申请日:2015-12-17

    Abstract: A display driving integrated circuit is provided which drives a plurality of gate lines included in a display panel. The display driving integrated circuit includes: a charge pump configured to change a voltage from an external power source to generate an output voltage; and a gate line driver configured to drive the plurality of gate lines based on the output voltage. The charge pump may operate in one of a low-current mode and a high-current mode based on a size of the display panel.

    Abstract translation: 提供一种显示驱动集成电路,其驱动包括在显示面板中的多个栅极线。 显示驱动集成电路包括:电荷泵,被配置为改变来自外部电源的电压以产生输出电压; 以及栅极线驱动器,被配置为基于所述输出电压来驱动所述多条栅极线。 基于显示面板的尺寸,电荷泵可以以低电流模式和高电流模式中的一种工作。

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