中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

27 records (took 0.017 seconds)

    METHOD OF GENERATING DEFECT CLASSIFICATION MODEL
    1.
    发明申请
    METHOD OF GENERATING DEFECT CLASSIFICATION MODEL 有权

    公开(公告)号：US20250037486A1

    公开(公告)日：2025-01-30

    申请号：US18668890

    申请日：2024-05-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jinwoo LEE ,  Bumjoo LEE ,  Jongcheon SUN ,  Suyoung LEE ,  Hyeongcheol LEE

    IPC: G06V20/69 ,  G06T7/00 ,  G06V10/764

    Abstract: A method of generating a defect classification model includes preparing a sample wafer that has undergone at least one unit of a manufacturing process, capturing, using an electronic device, a plurality of primary images of different locations of the sample wafer, obtaining a plurality of secondary images based on the capturing of the plurality of primary images, detecting a plurality of defect images including a defect from among the plurality of primary images and the plurality of secondary images, classifying and labeling at least one of the plurality of defect images as defect data, and generating an automatic defect classification model based on the defect data.

    MEMORY DEVICES
    2.
    发明公开
    MEMORY DEVICES 审中-公开

    公开(公告)号：US20240188305A1

    公开(公告)日：2024-06-06

    申请号：US18526031

    申请日：2023-12-01

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jinwoo LEE ,  Hyunchul SOHN ,  Jeongwoo LEE ,  Jaeyeon KIM ,  Kwangmin PARK ,  Dongho AHN ,  Jinmyung CHOI

    IPC: H10B63/00 ,  H10B63/10

    CPC classification number: H10B63/22 ,  H10B63/10 ,  H10B63/80

    Abstract: A memory device includes a substrate; a plurality of first conductive lines on the substrate and extending in a first direction; a plurality of second conductive lines on the plurality of first conductive lines and extending in a second direction crossing the first direction; and a plurality of first memory cells respectively arranged between the plurality of first conductive lines and the plurality of second conductive lines, wherein each first memory cell of the plurality of first memory cells includes a switching device and a variable resistance material pattern, and the switching device includes a material having a composition of LaxNi1-xOy, in which 0.13≤x≤0.30 and 0.9≤y≤1.5.

    SEMICONDUCTOR DEVICE
    6.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220069011A1

    公开(公告)日：2022-03-03

    申请号：US17209660

    申请日：2021-03-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dongho AHN ,  Segab KWON ,  Chungman KIM ,  Kwangmin PARK ,  Zhe WU ,  Seunggeun YU ,  Wonjun LEE ,  Jabin LEE ,  Jinwoo LEE

    IPC: H01L27/24 ,  H01L45/00

    Abstract: A semiconductor device includes a semiconductor substrate, a peripheral device on the semiconductor substrate, a lower insulating structure on the semiconductor substrate and covering the peripheral device, a first conductive line on the lower insulating structure, a memory cell structure on the first conductive line, and a second conductive line on the memory cell structure. The memory cell structure may include an information storage material pattern and a selector material pattern on the lower insulating structure in a vertical direction. The selector material pattern may include a first selector material layer including a first material and a second selector material layer including a second material. The second selector material layer may have a threshold voltage drift higher than that of the first material. The second selector material layer may have a second width narrower than a first width of the first selector material layer.

    SEMICONDUCTOR DEVICES
    10.
    发明申请
    SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20250014995A1

    公开(公告)日：2025-01-09

    申请号：US18663381

    申请日：2024-05-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jinwoo LEE ,  Hojun CHOI ,  Sutae KIM ,  Hyelim KIM ,  Seung CHOI

    IPC: H01L23/528 ,  H01L23/522 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

    Abstract: A semiconductor device includes a plurality of active patterns respectively extending on a substrate in a first direction, a separation pattern extending on the substrate in a second direction, and dividing each of the plurality of active patterns into first and second active patterns, the separation pattern including a first separation pattern and a second separation pattern, the second separation pattern being shifted from the first separation pattern in the first direction to partially overlap the first separation pattern in the second direction, first and second dummy gate structures on first and second sides of the separation pattern, respectively, and extending along corresponding end portions of the first and second active patterns in the second direction, respectively, and a plurality of first and second gate structures crossing portions of the first and second active patterns, respectively, and extending in the second direction.

Patent Agency Ranking