公开(公告)号：US20210357279A1

公开(公告)日：2021-11-18

申请号：US17198979

申请日：2021-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongyoung Lee ,  Dongyoon Kim ,  Minhyouk Kim ,  Jihyuk Oh ,  Insu Choi

IPC: G06F11/07 ,  G06F11/10 ,  G06F12/1036 ,  G06F9/455

Abstract: A method of operating a system running a virtual machine that executes an application and an operating system (OS) includes performing first address translation from first virtual addresses to first physical addresses, identifying faulty physical addresses among the first physical addresses, each faulty physical address corresponding to a corresponding first physical address associated with a faulty memory cell, analyzing a row address and a column address of each faulty physical address and specifying a fault type of the faulty physical addresses based on the analyzing of the row address and the column address of each faulty physical address, and performing second address translation from second virtual addresses to second physical addresses based on a faulty address, thereby excluding the faulty address from the second physical addresses.

公开(公告)号：US20210012831A1

公开(公告)日：2021-01-14

申请号：US16813962

申请日：2020-03-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihyuk Oh ,  Youngjin Park ,  Byoungjik Kim ,  Kiseok Park

IPC: G11C11/406 ,  G11C11/4076 ,  G11C11/4093 ,  G11C29/14 ,  G11C29/44

Abstract: A memory device includes a plurality of memory chips for writing and reading data in response to a control command and an address signal, and a control logic circuit for transferring the control command and the address signal to the plurality of the memory chips, and receiving a first command from a memory controller to perform a first operation, different from a refresh operation, on at least one of a plurality of the memory chips. The control logic circuit, in response to a refresh command, transmits the first command to at least one of a plurality of the memory chips and performs the first operation during a pre-determined refresh time interval without carrying out the refresh operation.

公开(公告)号：US11360837B2

公开(公告)日：2022-06-14

申请号：US17198979

申请日：2021-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongyoung Lee ,  Dongyoon Kim ,  Minhyouk Kim ,  Jihyuk Oh ,  Insu Choi

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/10 ,  G06F12/1036 ,  G06F9/455

Abstract: A method of operating a system running a virtual machine that executes an application and an operating system (OS) includes performing first address translation from first virtual addresses to first physical addresses, identifying faulty physical addresses among the first physical addresses, each faulty physical address corresponding to a corresponding first physical address associated with a faulty memory cell, analyzing a row address and a column address of each faulty physical address and specifying a fault type of the faulty physical addresses based on the analyzing of the row address and the column address of each faulty physical address, and performing second address translation from second virtual addresses to second physical addresses based on a faulty address, thereby excluding the faulty address from the second physical addresses.

公开(公告)号：US11328786B2

公开(公告)日：2022-05-10

申请号：US16781184

申请日：2020-02-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihyuk Oh ,  Jiseok Kang ,  Junho Jung

IPC: G11C29/10 ,  G06F13/16

Abstract: A memory module includes at least one semiconductor memory device, and a test pattern memory that stores first test pattern information for testing the at least one semiconductor memory device, and the first test pattern information stored in the test pattern memory is transferred to a host in a test operation. Through the memory module having the above-described function, a memory test is possible in consideration of a unique weak characteristic of the memory module.

公开(公告)号：US10978133B2

公开(公告)日：2021-04-13

申请号：US16813962

申请日：2020-03-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihyuk Oh ,  Youngjin Park ,  Byoungjik Kim ,  Kiseok Park

IPC: G11C11/406 ,  G11C29/44 ,  G11C11/4093 ,  G11C29/14 ,  G11C11/4076

Abstract: A memory device includes a plurality of memory chips for writing and reading data in response to a control command and an address signal, and a control logic circuit for transferring the control command and the address signal to the plurality of the memory chips, and receiving a first command from a memory controller to perform a first operation, different from a refresh operation, on at least one of a plurality of the memory chips. The control logic circuit, in response to a refresh command, transmits the first command to at least one of a plurality of the memory chips and performs the first operation during a pre-determined refresh time interval without carrying out the refresh operation.